Author: Israel KorenPublisher:
ISBN:
Category :
Languages : en
Pages : 70
Book Description
Describes fault-tolerance and yield improvement techniques in relation to VLSI processor arrays.
Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multiprocessing Systems
Author: Israel KorenPublisher:
ISBN:
Category :
Languages : en
Pages : 70
Book Description
Describes fault-tolerance and yield improvement techniques in relation to VLSI processor arrays.
Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multi-Precessor Systems
Author: Israel KorenPublisher:
ISBN:
Category :
Languages : en
Pages : 52
Book Description
New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emergent area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance, and yield improvement techniques. Fault-tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault-tolerance at work in these multi-processor systems. These precepts are useful to then present certain techniques that will incorporate fault-tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques. (Author).
Defect and Fault Tolerance in VLSI Systems
Author: Israel KorenPublisher: Springer Science & Business Media
ISBN: 1461567998
Category : Computers
Languages : en
Pages : 362
Book Description
This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.
Fault-Tolerant Systems
Author: Israel KorenPublisher: Morgan Kaufmann
ISBN: 0128181060
Category : Computers
Languages : en
Pages : 418
Book Description
Fault-Tolerant Systems, Second Edition, is the first book on fault tolerance design utilizing a systems approach to both hardware and software. No other text takes this approach or offers the comprehensive and up-to-date treatment that Koren and Krishna provide. The book comprehensively covers the design of fault-tolerant hardware and software, use of fault-tolerance techniques to improve manufacturing yields, and design and analysis of networks. Incorporating case studies that highlight more than ten different computer systems with fault-tolerance techniques implemented in their design, the book includes critical material on methods to protect against threats to encryption subsystems used for security purposes. The text’s updated content will help students and practitioners in electrical and computer engineering and computer science learn how to design reliable computing systems, and how to analyze fault-tolerant computing systems. Delivers the first book on fault tolerance design with a systems approach Offers comprehensive coverage of both hardware and software fault tolerance, as well as information and time redundancy Features fully updated content plus new chapters on failure mechanisms and fault-tolerance in cyber-physical systems Provides a complete ancillary package, including an on-line solutions manual for instructors and PowerPoint slides
Scientific and Technical Aerospace Reports
Author: Parallel Algorithms and Architectures for DSP Applications
Author: Magdy A. BayoumiPublisher: Springer Science & Business Media
ISBN: 146153996X
Category : Technology & Engineering
Languages : en
Pages : 289
Book Description
Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac ceptable speed performance.
Design And Analysis Of Reliable And Fault-tolerant Computer Systems
Author: Mostafa I Abd-el-barrPublisher: World Scientific
ISBN: 190897978X
Category : Computers
Languages : en
Pages : 463
Book Description
Covering both the theoretical and practical aspects of fault-tolerant mobile systems, and fault tolerance and analysis, this book tackles the current issues of reliability-based optimization of computer networks, fault-tolerant mobile systems, and fault tolerance and reliability of high speed and hierarchical networks.The book is divided into six parts to facilitate coverage of the material by course instructors and computer systems professionals. The sequence of chapters in each part ensures the gradual coverage of issues from the basics to the most recent developments. A useful set of references, including electronic sources, is listed at the end of each chapter./a
Systolic Algorithms
Author: David J. EvansPublisher: CRC Press
ISBN: 9782881248047
Category : Mathematics
Languages : en
Pages : 466
Book Description
While the architecture of present-day parallel supercomputers is largely based on the concept of a shared memory, with its attendant limitations of common access, advances in semicoductor technology have led to the development of highly parellel computer architectures with decentralized storage and limited connections in which each processor possesses high bandwidth local memory connected to a small number of such architectures, enabling cost-effective high-speed parallel processing for large volumes of data, with ultra-high throughput rates. Algorithms suitable for implementation on systolic arrays find applications in areas such as signal and image processing, pattern matching, linear algebra, recurrence algorithms and graph problems. This book provides an insight into the implementation of systolic arrays and gives a comprehensive overview of the techniques and theories contributing to the design of systolic algorithms.
Proceedings / Parcella 1988
Author: Gottfried WolfPublisher: Springer Science & Business Media
ISBN: 9783540506478
Category : Computers
Languages : en
Pages : 386
Book Description
Proceedings -- Parallel Computing.
Author: