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Author: Cheng-Chi Wong Publisher: Springer Science & Business Media ISBN: 1461483107 Category : Technology & Engineering Languages : en Pages : 106
Book Description
This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.
Author: Cheng-Chi Wong Publisher: Springer Science & Business Media ISBN: 1461483107 Category : Technology & Engineering Languages : en Pages : 106
Book Description
This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.
Author: Aliazam Abbasfar Publisher: Springer Science & Business Media ISBN: 1402063911 Category : Technology & Engineering Languages : en Pages : 94
Book Description
This book introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps).
Author: Keattisak Sripimanwat Publisher: Springer Science & Business Media ISBN: 140203685X Category : Technology & Engineering Languages : en Pages : 393
Book Description
Turbo Code Applications: a journey from a paper to realization presents c- temporary applications of turbo codes in thirteen technical chapters. Each chapter focuses on a particular communication technology utilizing turbo codes, and they are written by experts who have been working in related th areas from around the world. This book is published to celebrate the 10 year anniversary of turbo codes invention by Claude Berrou Alain Glavieux and Punya Thitimajshima (1993-2003). As known for more than a decade, turbo code is the astonishing error control coding scheme which its perf- mance closes to the Shannon’s limit. It has been honored consequently as one of the seventeen great innovations during the ?rst ?fty years of information theory foundation. With the amazing performance compared to that of other existing codes, turbo codes have been adopted into many communication s- tems and incorporated with various modern industrial standards. Numerous research works have been reported from universities and advance companies worldwide. Evidently, it has successfully revolutionized the digital commu- cations. Turbo code and its successors have been applied in most communications startingfromthegroundorterrestrialsystemsofdatastorage,ADSLmodem, and ?ber optic communications. Subsequently, it moves up to the air channel applications by employing to wireless communication systems, and then ?ies up to the space by using in digital video broadcasting and satellite com- nications. Undoubtedly, with the excellent error correction potential, it has been selected to support data transmission in space exploring system as well.
Author: Vianney Lapôtre Publisher: ISBN: Category : Languages : en Pages : 129
Book Description
Recent years have seen a huge evolution of wireless communication standards in the domains of mobile phone, local and wide area networks and video broadcasting. These evolutions aim at increasing the requirements in terms of throughput, robustness against destructive channel effects and convergence of services in a smart terminal. As an example, the fourth generation (4G) of cellular wireless standards aims at providing mobile broadband solution to laptop computer wireless modems, smartphones, and other mobile devices. Diverse features such as ultra-broadband Internet access, IP telephony, gaming services, and streamed multimedia are provided. In order to enable such advanced services at the algorithmic level, new state of the art data processing techniques have been developed and adopted in the emerging wireless communication standards. At the architecture level, many efforts are being conducted towards the design of flexible high throughput hardware platforms which can be configured to the required configuration. In order to reach high flexibility, the I.A.S. (Algorithm Silicon Interaction) team of the Lab-STICC laboratory has developed an Application Specific Instruction Set Processor (ASIP) based multi-standard multiprocessor Turbo decoder. This architecture is based on the DecASIP processor. Previous work provides an efficient way to reach the high performance and high flexibility requirements of emergent standards. However, dynamic reconfiguration aspect of the architecture has not been addressed. In this context, this Ph.D work targets the development of a dynamically reconfigurable multiprocessor Turbo decoder for future communication standards. For that purpose, this thesis work is divided in several steps. The first step consists on the study of the initial processor architecture in order to propose optimizations in a multiprocessor context. This step leads to a new implementation of the DecASIP processor integrating a new configuration memory organization in order to reduce the configuration transfer latency. The second step leads to the development of a configuration infrastructure allowing an efficient and high speed configuration transfer for the ASIPs and the controller of the platform. The proposed approach is based on a low complexity unidirectional pipeline bus implementing optimized transfer mechanisms such as multicast and broadcast. This configuration infrastructure provides an efficient solution in order to transfer an entire configuration for 128 processors in less than one microsecond. Finally, the last step of this thesis work concerns the development of a configuration management of the proposed platform in order to adapt the configuration parameters regarding the environment evolution and the application requirements. This step leads on an approach allowing the support of dynamic configuration of the platform in the context of highly constrained scenario in terms of throughput and error rate performances where each frame or group of frames is associated to a specific configuration. This thesis work will allow the laboratory to present a prototype of a dynamically reconfigurable Turbo decoder respecting future communication standards requirements in terms of flexibility, throughput and error rate performances. Such a contribution gathers the skills present in the Lab-STICC laboratory at the decoding algorithm, multiprocessor architecture, dynamic reconfiguration and self-adaptation levels in a single prototype.
Author: Matthieu Arzel Publisher: ISBN: Category : Languages : en Pages : 152
Book Description
Over the past decade, telecommunication systems have dramatically grown providing services which require ever more data rate with ever more mobility. To sustain this growth, enhanced and new techniques were implemented in ever more optimised digital circuits. A novel approach could be soon necessary for some of these techniques, due to the limitations of their hardware implementations. Error correction is one of them. It allows to reduce the energy used to send information, but, when implemented on a chip, it is a bottleneck in terms of data throughput and of, paradoxically, power consumption. The analogue iterative decoding could solve this problem. This technique, promising high performance, requires new architectures and codes adapted to the constraints of analogue processing to challenge digital circuits in the field of industrial applications. A novel architecture and a novel turbo decoding algorithm, offering a good compromise between onchip area and data rate, are proposed in this thesis. They pave the way for integrating flexible high-speed analogue turbo decoders dealing with different frame lengths ranging from a few dozen to a few thousand bits. The new architecture and decoding algorithm are applied to a DVB-RCS-like code. The component 8-state decoder used in this new architecture was designed for a 0.25μm BiCMOS process. Dealing with frames made up of 24 double-binary symbols, it is, up to this date, one of the most complex analogue decoders ever designed. Implemented on chip, the circuit was successfully tested at 100Mbit/s while consuming 414mW on a 2.8V analogue core supply. It was shown to provide a bit error rate as close as 0.3dB to the digital one.
Author: Cyrille Chavet Publisher: Springer ISBN: 3319105698 Category : Technology & Engineering Languages : en Pages : 197
Book Description
This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.
Author: Manfred Glesner Publisher: Springer ISBN: 3540461175 Category : Computers Languages : en Pages : 1209
Book Description
This book constitutes the refereed proceedings of the 12th International Conference on Field-Programmable Logic and Applications, FPL 2002, held in Montpellier, France, in September 2002. The 104 revised regular papers and 27 poster papers presented together with three invited contributions were carefully reviewed and selected from 214 submissions. The papers are organized in topical sections on rapid prototyping, FPGA synthesis, custom computing engines, DSP applications, reconfigurable fabrics, dynamic reconfiguration, routing and placement, power estimation, synthesis issues, communication applications, new technologies, reconfigurable architectures, multimedia applications, FPGA-based arithmetic, reconfigurable processors, testing and fault-tolerance, crypto applications, multitasking, compilation techniques, etc.
Author: Wolfgang Eberle Publisher: Springer Science & Business Media ISBN: 0387745165 Category : Technology & Engineering Languages : en Pages : 296
Book Description
The fields of communication, signal processing, and embedded systems and circuits are brought together in this book. These fields come together with a single design goal, a WLAN transceiver which combines analog and digital design, VLSI and systems design, algorithms and architectures, as well as design and CAD/EDA. This book focuses on the overall approach to design problems and design organization needed for transceiver design. It does not focus on one particular standard.
Author: Adibi, Sasan Publisher: IGI Global ISBN: 1615206752 Category : Business & Economics Languages : en Pages : 836
Book Description
Fourth-Generation Wireless Networks: Applications and Innovations presents a comprehensive collection of recent findings in access technologies useful in the architecture of wireless networks.
Author: Cheng-Chi Wong
Author: Cheng-Chi Wong
Author: Aliazam Abbasfar
Author: Keattisak Sripimanwat
Author: Vianney Lapôtre
Author: Matthieu Arzel
Author: Cyrille Chavet
Author: Manfred Glesner
Author: Wolfgang Eberle
Author: 
Author: Adibi, Sasan