Author: University of Minnesota. Computer Science Dept
Publisher:
ISBN:
Category : Computer networks
Languages : en
Pages : 20
Book Description
Abstract: "It is shown that for a tree of cells for which the fault-free tree cannot produce all combinations at the output of each cell, there is only the trivial test set for multiple faults. It is also shown that a tree-structured design of the parallel carry lookahead adder only has the trivial test set for multiple faults, based on the fact that the cells in the tree cannot generate a fault-free output (1,1). Also, a formula is given for a multiple fault detection test set for the parallel carry lookahead adder under the assumption that the faulty parallel adder cannot generate a faulty output (1,1) at any of its processors."
Multiple Fault Detection in Tree-structured Combinational Networks
Author: University of Minnesota. Computer Science Dept
Publisher:
ISBN:
Category : Computer networks
Languages : en
Pages : 20
Book Description
Abstract: "It is shown that for a tree of cells for which the fault-free tree cannot produce all combinations at the output of each cell, there is only the trivial test set for multiple faults. It is also shown that a tree-structured design of the parallel carry lookahead adder only has the trivial test set for multiple faults, based on the fact that the cells in the tree cannot generate a fault-free output (1,1). Also, a formula is given for a multiple fault detection test set for the parallel carry lookahead adder under the assumption that the faulty parallel adder cannot generate a faulty output (1,1) at any of its processors."
Publisher:
ISBN:
Category : Computer networks
Languages : en
Pages : 20
Book Description
Abstract: "It is shown that for a tree of cells for which the fault-free tree cannot produce all combinations at the output of each cell, there is only the trivial test set for multiple faults. It is also shown that a tree-structured design of the parallel carry lookahead adder only has the trivial test set for multiple faults, based on the fact that the cells in the tree cannot generate a fault-free output (1,1). Also, a formula is given for a multiple fault detection test set for the parallel carry lookahead adder under the assumption that the faulty parallel adder cannot generate a faulty output (1,1) at any of its processors."
Multiple Fault Detection in Combinational Network Topologies
Multiple Fault Detection in combinational networks
Automated Multiple Fault Test Generation for Combinational Networks
Author: Robert A. Hendrix
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.
Multiple Fault Detection in Combinational Circuits
IEEE VLSI Test Symposium
Author:
Publisher:
ISBN:
Category : Application-specific integrated circuits
Languages : en
Pages : 552
Book Description
Publisher:
ISBN:
Category : Application-specific integrated circuits
Languages : en
Pages : 552
Book Description
Fault Analysis of Combinational Logic Networks
Author: Lung-Hsiung Chang
Publisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 248
Book Description
Publisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 248
Book Description
Multiple Fault Detection in Combinational Circuits
Author: Sivanarayana Mallela
Publisher:
ISBN:
Category :
Languages : en
Pages : 128
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 128
Book Description
NIST Special Publication
Author:
Publisher:
ISBN:
Category : Weights and measures
Languages : en
Pages : 228
Book Description
Publisher:
ISBN:
Category : Weights and measures
Languages : en
Pages : 228
Book Description
Multiple Fault Diagnosis in Combinational Networks
Author: Charles Wei-Yuan Cha
Publisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Publisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.