Author: Zhongfeng WangPublisher:
ISBN:
Category :
Languages : en
Pages : 396
Book Description
High Performance,low Complexity VLSI Design of Turbo Decoders
Author: Zhongfeng WangTurbo-like Codes
Author: Aliazam AbbasfarPublisher: Springer Science & Business Media
ISBN: 1402063911
Category : Technology & Engineering
Languages : en
Pages : 94
Book Description
This book introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps).
VLSI Architectures for Turbo Code Decoders, LDPC Code Decoders and List Sphere Decoders
Author: Yuping ZhangTurbo Decoder Architecture for Beyond-4G Applications
Author: Cheng-Chi WongPublisher: Springer Science & Business Media
ISBN: 1461483107
Category : Technology & Engineering
Languages : en
Pages : 106
Book Description
This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards in multiple parallel modes. Moreover, some solutions that can overcome the limitation upon the speedup of parallel architecture by modification to turbo codec are presented here. Compared to the traditional designs, these methods can lead to at most 33% gain in throughput with similar performance and similar cost.
Low Complexity, High Speed VLSI Architectures for Error Correction Decoders
Author: Yanni ChenReduced Complexity Decoding and Relative Performance of Turbo Codes
Author: Chi Wa LeongHigh-Throughput Turbo Decoder Design with Low-Complexity Interleaver for 3GPP-LTE/LTE-A Systems
Author: 劉忠艷Reduced Complexity Decoding and Relative Performance of Turbo Codes
Author: Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
The thesis has two main topics, both related to turbo codes. The first one deals with the design of reduced complexity decoding of turbo codes. In particular, two new decoders are designed using ideas from the M-algorithm: one to decode the constituent code and the other the entire turbo code. Both decoders are found to be suitable only for short turbo codes with information block size less than 300 bits. For these turbo codes the two decoders have a lower complexity with a small degradation in error performance when compared to the original decoder used to decode the turbo codes. Therefore they are recommended in applications where short turbo codes are used and a small processing delay is required. The second topic of the thesis is whether the turbo code is superior to any other code. A partial answer is found by comparing short BCH codes to turbo codes with similar parameters. It is found that the BCH codes are more attractive than the turbo codes in both decoding complexity and error performance. This implies that traditional block codes are better than turbo codes with similar parameters.
Low-complexity High-speed VLSI Design of Low-density Parity-check Decoders
Author: Zhiqiang CuiPublisher:
ISBN:
Category : Decoders (Electronics)
Languages : en
Pages : 218
Book Description
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g., N>1000 bits), which lead to a linear increase of the size of memory for storing all the soft messages in LDPC decoding. In the next generation communication systems, the target data rates range from a few hundred Mbit/sec to several Gbit/sec. To achieve those very high decoding throughput, a large amount of computation units are required, which will significantly increase the hardware cost and power consumption of LDPC decoders. LDPC codes are decoded using iterative decoding algorithms. The decoding latency and power consumption are linearly proportional to the number of decoding iterations. A decoding approach with fast convergence speed is highly desired in practice. This thesis considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory requirement, low complexity implementation, and high speed decoding of LDPC codes. We propose a memory efficient partially parallel decoder architecture suited for quasi-cyclic LDPC (QC-LDPC) codes using Min-Sum decoding algorithm. We develop an efficient architecture for general permutation matrix based LDPC codes. We have explored various approaches to linearly increase the decoding throughput with a small amount of hardware overhead. We develop a multi-Gbit/sec LDPC decoder architecture for QC-LDPC codes and prototype an enhanced partially parallel decoder architecture for a Euclidian geometry based LDPC code on FPGA. We propose an early stopping scheme and an extended layered decoding method to reduce the number of decoding iterations for undecodable and decodable sequence received from channel. We also propose a low-complexity optimized 2-bit decoding approach which requires comparable implementation complexity to weighted bit flipping based algorithms but has much better decoding performance and faster convergence speed.
Author: