Fault Masking in Combinational Logic Circuits PDF Download

Author: Stanford University Stanford Electronics Laboratories. Digital Systems Laboratory
Publisher:
ISBN:
Category :
Languages : en
Pages : 40

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Author: Marion S. Dunning
Publisher:
ISBN:
Category :
Languages : en
Pages : 72

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Book Description
The current study continues the comparison of quadded and restored trees. Explicit equations were derived for computing the signal-state reliability which is defined as the probability of correct output for a given function and a given assignment of values to the variables averaged over all variable assignments and all functions. An investigation was made of a new logical structure composed uniformly of diodes. We call the structure a v sub q-module. The v sub q-module, like the micro sub q-module, is capable of executing all functions of q variables. Function selection is also made by applying constant signals to the 2 super scrip q boundary control lines and failure of any component results in the improper execution of at least one of the 2 superscrip 2q functions. The tree which executes all functions of n variables is built out of v sub q-modules and v sub r-modules, where n = pq + r for some p, and is called the n-variable (q+l)-input AND-OR tree. An optimization study was made to find the q and r for a given n which result in the most reliable n-variable AND-OR tree. Three failure models of the diode were studied and for each a redundance scheme is introduced which renders any homogeneous logic structure composed of diodes arbitrarily reliable. If the diode is open with probability alpha, we replace it by m diodes in parallel. If the diode shorts with probability beta, we replace it by m diodes in parallel. If the diode is open with probability alpha and shorted with probability beta, then it is replaced by a series-parallel or parallel-series array of diodes.

Author: Parag K. Lala
Publisher: Academic Press
ISBN: 9780124343306
Category : Computers
Languages : en
Pages : 222

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Book Description
An easy to use introduction to the practices and techniques in the field of digital circuit testing. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.

Author:
Publisher:
ISBN:
Category : Physical instruments
Languages : en
Pages : 52

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Author: Virendra Singh Negi
Publisher:
ISBN:
Category : Electric circuits
Languages : en
Pages : 100

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Author: Muhammad Yasin
Publisher: Springer Nature
ISBN: 3030153347
Category : Technology & Engineering
Languages : en
Pages : 142

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Book Description
With the popularity of hardware security research, several edited monograms have been published, which aim at summarizing the research in a particular field. Typically, each book chapter is a recompilation of one or more research papers, and the focus is on summarizing the state-of-the-art research. Different from the edited monograms, the chapters in this book are not re-compilations of research papers. The book follows a pedagogical approach. Each chapter has been planned to emphasize the fundamental principles behind the logic locking algorithms and relate concepts to each other using a systematization of knowledge approach. Furthermore, the authors of this book have contributed to this field significantly through numerous fundamental papers.

Author: Smita Krishnaswamy
Publisher: Springer Science & Business Media
ISBN: 9048196442
Category : Technology & Engineering
Languages : en
Pages : 130

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Book Description
Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

Author: P. Antognetti
Publisher: Springer Science & Business Media
ISBN: 9401180067
Category : Technology & Engineering
Languages : en
Pages : 543

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Book Description
The Nato Advanced Study Institute on "Computer Design Aids for VLSI Circuits" was held from July 21 to August 1, 1980 at Sogesta, Urbino, Italy. Sixty-three carefully chosen profes sionals were invited to participate in this institute together with 12 lecturers and 7 assistants. The 63 participants were selected from a group of almost 140 applicants. Each had the background to learn effectively the set of computer IC design aids which were presented. Each also had individual expertise in at least one of the topics of the Institute. The Institute was designed to provide hands-on type of experience rather than consisting of solely lecture and discussion. Each morning, detailed presentations were made concerning the critical algorithms that are used in the various types of computer IC design aids. Each afternoon a lengthy period was used to provide the participants with direct access to the computer programs. In addition to using the programs, the individual could, if his expertise was sufficient, make modifications of and extensions to the programs, or establish limitations of these present aids. The interest in this hands-on activity was very high and many participants worked with the programs every free hour. The editors would like to thank the Direction of SOGESTA for the excellent facilities, ~1r. R. Riccioni of the SOGESTA Computer Center and Mr. 11. Vanzi of the University of Genova for enabling all the programs to run smoothly on the set date. P.Antognetti D.O.Pederson Urbino, Summer 1980.

Author: Smita Krishnaswamy
Publisher: Springer Science & Business Media
ISBN: 9048196434
Category : Technology & Engineering
Languages : en
Pages : 130

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Book Description
Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

Author: Shamria Sabatina Latif
Publisher:
ISBN:
Category :
Languages : en
Pages :

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Book Description
In recent years reversible logic has offered a promising alternative to traditional logic circuits. Reversible logic introduces a mechanism which allows theoretically zero energy dissipation by eliminating the possibility of information loss. However, it is also desirable that all computation should ideally be done in a fault tolerant manner. To address this we propose techniques to achieve fault tolerance in reversible logic based on a passive hardware redundancy technique. We propose two new designs for a reversible majority voter circuit that can be used to implement fault masking. Comparisons to existing designs are presented in terms of cost metrics such as gate count, garbage outputs, constant inputs, and quantum cost. Comparative failure probability analysis of the proposed voter circuits is also provided. Simulation results of the voter circuit failure probabilities over different numbers of trials are also presented. Our approach can be used to determine the circuit failure probability by using the gate failure probabilities. The proposed methodology can provide useful information for future reversible gate fabrication and designing future fault tolerant reversible circuits.