Author: Patrick Jonathan TaylorPublisher:
ISBN:
Category :
Languages : en
Pages : 322
Book Description
Fabrication of Reduced Dislocation Density GaAs on Si by Stoichiometric Low-temperature Epitaxial Growth
Author: Patrick Jonathan TaylorPublisher:
ISBN:
Category :
Languages : en
Pages : 322
Book Description
Low Temperature Epitaxial Growth of Semiconductors
Author: Takashi HariuPublisher: World Scientific
ISBN: 9789971508395
Category : Technology & Engineering
Languages : en
Pages : 356
Book Description
Low temperature processes for semiconductors have been recently under intensive development to fabricate controlled device structures with minute dimensions in order to achieve the highest device performance and new device functions as well as high integration density. Comprising reviews by experts long involved in the respective pioneering work, this volume makes a useful contribution toward maturing the process of low temperature epitaxy as a whole.
Epitaxial Growth of Si(Ge) Materials on Si and GaAs by Low Temperature PECVD: Towards Tandem Devices
Author: Romain CariouEpitaxial Silicon Technology
Author: B BaligaPublisher: Elsevier
ISBN: 0323155456
Category : Technology & Engineering
Languages : en
Pages : 337
Book Description
Epitaxial Silicon Technology is a single-volume, in-depth review of all the silicon epitaxial growth techniques. This technology is being extended to the growth of epitaxial layers on insulating substrates by means of a variety of lateral seeding approaches. This book is divided into five chapters, and the opening chapter describes the growth of silicon layers by vapor-phase epitaxy, considering both atmospheric and low-pressure growth. The second chapter discusses molecular-beam epitaxial growth of silicon, providing a unique ability to grow very thin layers with precisely controlled doping characteristics. The third chapter introduces the silicon liquid-phase epitaxy, in which the growth of silicon layers arose from a need to decrease the growth temperature and to suppress autodoping. The fourth chapter addresses the growth of silicon on sapphire for improving the radiation hardness of CMOS integrated circuits. The fifth chapter deals with the advances in the application of silicon epitaxial growth. This chapter also discusses the formation of epitaxial layers of silicon on insulators, such as silicon dioxide, which do not provide a natural single crystal surface for growth. Each chapter begins with a discussion on the fundamental transport mechanisms and the kinetics governing the growth rate, followed by a description of the electrical properties that can be achieved in the layers and the restrictions imposed by the growth technique upon the control over its electrical characteristics. Each chapter concludes with a discussion on the applications of the particular growth technique. This reference material will be useful for process technologists and engineers who may need to apply epitaxial growth for device fabrication.
Selective SiGe Nanostructures
Author: Thomas Andrew LangdoPublisher:
ISBN:
Category : Nanostructured materials
Languages : en
Pages : 220
Book Description
(Cont.) By a combination of interferometric lithography Si/SiO2 substrate patterning and Ge selective epitaxial growth, we have demonstrated threading dislocation blocking at the oxide sidewall which shows promise for dislocation filtering and the fabrication of low defect density Ge on Si for III-V device integration. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth (ELO) fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in any lattice-mismatched systems where dislocations are not parallel to growth directions. Investigation of Ge selective growth in micron-sized SiO2 features by plan-view TEM shows that substrate patterning on the order of microns is insufficient to filter dislocations in a large mismatch system ([epsilon]> 2%). Ge p-i-n photodetectors were selectively grown in micron-sized SiO2/Si features to correlate materials properties with electrical characteristics. For chemical protection and compatibility with Si microelectronics, Ge photodetector regions were capped with a thin n+ Si layer. Photodetectors fabricated on unpatterned substrates demonstrated leakage currents comparable to published results on Ge on Si photodetectors while leakage currents were noticeably degraded in devices grown on patterned substrates.
Microstructural Investigation of Defects in Epitaxial GaAs Grown on Mismatched Ge and SiGe/Si Substrates
Author: Boeckl John J.Publisher:
ISBN:
Category : Gallium arsenide
Languages : en
Pages :
Book Description
Abstract: In this dissertation we report on the structural quality of the GaAs/Ge interface for GaAs nucleation by solid source molecular beam epitaxy (MBE). Through feedback from these characterizations, optimized growth methods are established, demonstrating the ability to grow defect-free epitaxial GaAs films on Ge substrates. We also present data on the electrical activity associated with defects that result if the growth is not fully controlled. In theses studies we exploit a novel use of an electron beam induced current (EBIC) technique to show the electrical activity associated with anti-phase domains and inter-diffusion from regions as small as 100 nm. Integrating this GaAs MBE nucleation methodology on the SiGe graded substrates we show that the GaAs stoichiometry and material properties transfer without degradation from the higher threading dislocation density of the SiGe substrates. In these studies we show that fundamental defects such as; threading dislocation, anti-phase domains, and atomic inter-diffusion are controlled to a level that enables growth of extremely high quality GaAs device layers. Combined with the low TDD enabled by the SiGe graded buffer, record GaAs/Si minority carrier lifetimes in excess of 10 ns have been achieved. However, other larger scale defects are shown to have a limiting effect on large area device performance. One such morphological surface defect, known as the "bat", is generated during the UHVCVD SiGe growth. The defect was comprehensively studied and results indicate that the impact on GaAs device performance was due to dislocation clusters in MBE device layers. Comparison analysis with GaAs overgrowth via metal organic chemical vapor deposition (MOCVD) demonstrated this growth method produced fully-operational large-area device structure. A model relating surface growth rates to an incomplete lattice-mismatch relaxation predicts the formation of these clusters. While challenges remain for monolithic III/V optoelectronic integration on Si, it is clear that the demonstration of successful GaAs nucleation on the SiGe substrate represents a significant milestone on the path to the final goal of truly integrated III-V devices with Si integrated circuits.
Electrical & Electronics Abstracts
Author: Publisher:
ISBN:
Category : Electrical engineering
Languages : en
Pages : 1904
Book Description
Energy Research Abstracts
Author: Defect Reduction in Epitaxial Growth Using Superlattice Buffer Layers
Author: S. M. BedairPublisher:
ISBN:
Category :
Languages : en
Pages : 20
Book Description
Several superlattice structures, grown by molecular beam epitaxy, have been used to reduce the density of threading dislocations originating from the Gallium Arsenide substrates. Initial results indicate that GaAsP-InGaAs strained layer superlattice buffer layers are effective in reducing dislocation in GaAs grown on silicon substrates. The stability of SLS in electronic devices either as part of the active layers or buffer layers is being addressed. We are currently conducting pioneering work in new ways to deposit superlattices and atomic layer epitaxy without any gas switching.
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium
Author: Publisher: Institute of Electrical & Electronics Engineers(IEEE)
ISBN:
Category : Electronic apparatus and appliances
Languages : en
Pages : 520
Book Description