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Author: Hong Dongwoo Publisher: Springer ISBN: 9789048134595 Category : Computers Languages : en Pages : 98
Book Description
Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.
Author: Hong Dongwoo Publisher: Springer ISBN: 9789048134595 Category : Computers Languages : en Pages : 98
Book Description
Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.
Author: Dongwoo Hong Publisher: Springer Science & Business Media ISBN: 9048134439 Category : Computers Languages : en Pages : 104
Book Description
Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.
Author: Cecilia Gimeno Gasca Publisher: Springer ISBN: 3319105639 Category : Technology & Engineering Languages : en Pages : 164
Book Description
This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).
Author: Yongquan Fan Publisher: Springer Science & Business Media ISBN: 9048193982 Category : Technology & Engineering Languages : en Pages : 200
Book Description
High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces. Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.
Author: Ujjwal Guin Publisher: ISBN: Category : Languages : en Pages : 78
Book Description
High-speed serial links in modern communication systems often require the Bit-Error-Rate (BER) to be at the level of 10 −12 or lower. From the industry perspective, major drawbacks in high volume production test for the serial links with low BER are the excessive test time for comparing each captured bit for error detection and costly instrumentation. In this thesis, we focus on developing a novel BER estimation methodology and its implementation. We propose a novel BER estimation methodology and an effective self-test system, which not only eliminates the usage of expensive measuring instruments, but also significantly reduces the test time. In the proposed BER estimation, we show that the total jitter (TJ) spectral information of a test SerDes is successfully estimated from the known TJ distribution of a golden SerDes. We propose a novel BER estimation formula that incorporates not only the TJ spectral information of the serial data, but also the TJ spectral information of the recovered clock. Our proposed estimation formula enables efficient BER estimation without excessive test time, and its accuracy does not depend on the jitter present in the serial data stream of the SerDes. The experimental results demonstrate that the test time for the proposed BER estimation is in the order of seconds, which translates to the test time savings of more than hundred times compared to the traditional BER measurement for the same accuracy. To implement the proposed BER estimation methodology, we have developed a novel time-to-digital converter (TDC). This design effectively measures the delay between two signals and converts it into the digital format. Performance of the TDC has been evaluated and presented using ModelSim and SPICE simulation.
Author: Jose Moreira Publisher: Artech House ISBN: 1608079864 Category : Technology & Engineering Languages : en Pages : 709
Book Description
This second edition of An Engineer's Guide to Automated Testing of High-Speed Interfaces provides updates to reflect current state-of-the-art high-speed digital testing with automated test equipment technology (ATE). Featuring clear examples, this one-stop reference covers all critical aspects of automated testing, including an introduction to high-speed digital basics, a discussion of industry standards, ATE and bench instrumentation for digital applications, and test and measurement techniques for characterization and production environment. Engineers learn how to apply automated test equipment for testing high-speed digital I/O interfaces and gain a better understanding of PCI-Express 4, 100Gb Ethernet, and MIPI while exploring the correlation between phase noise and jitter. This updated resource provides expanded material on 28/32 Gbps NRZ testing and wireless testing that are becoming increasingly more pertinent for future applications. This book explores the current trend of merging high-speed digital testing within the fields of photonic and wireless testing.
Author: Long Jin Publisher: Frontiers Media SA ISBN: 2832552013 Category : Science Languages : en Pages : 301
Book Description
Neural network control has been a research hotspot in academic fields due to the strong ability of computation. One of its wildly applied fields is robotics. In recent years, plenty of researchers have devised different types of dynamic neural network (DNN) to address complex control issues in robotics fields in reality. Redundant manipulators are no doubt indispensable devices in industrial production. There are various works on the redundancy resolution of redundant manipulators in performing a given task with the manipulator model information known. However, it becomes knotty for researchers to precisely control redundant manipulators with unknown model to complete a cyclic-motion generation CMG task, to some extent. It is worthwhile to investigate the data-driven scheme and the corresponding novel dynamic neural network (DNN), which exploits learning and control simultaneously. Therefore, it is of great significance to further research the special control features and solve challenging issues to improve control performance from several perspectives, such as accuracy, robustness, and solving speed.
Author: Mike Peng Li Publisher: Pearson Education ISBN: 0132797194 Category : Technology & Engineering Languages : en Pages : 443
Book Description
State-of-the-art JNB and SI Problem-Solving: Theory, Analysis, Methods, and Applications Jitter, noise, and bit error (JNB) and signal integrity (SI) have become today‘s greatest challenges in high-speed digital design. Now, there’s a comprehensive and up-to-date guide to overcoming these challenges, direct from Dr. Mike Peng Li, cochair of the PCI Express jitter standard committee. One of the field’s most respected experts, Li has brought together the latest theory, analysis, methods, and practical applications, demonstrating how to solve difficult JNB and SI problems in both link components and complete systems. Li introduces the fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes. He guides readers from basic math, statistics, circuit and system models all the way through final applications. Emphasizing clock and serial data communications applications, he covers JNB and SI simulation, modeling, diagnostics, debugging, compliance testing, and much more.
Author: Hong Dongwoo
Author: Hong Dongwoo
Author: Dongwoo Hong
Author: Cecilia Gimeno Gasca
Author: Yongquan Fan
Author: Ujjwal Guin
Author: Jose Moreira
Author: Long Jin
Author: 
Author: Mike Peng Li
Author: