Design of LDPC Decoders for Improved Low Error Rate Performance PDF Download

Author: Zhengya Zhang
Publisher:
ISBN:
Category :
Languages : en
Pages : 330

View

Book Description

Author: Vikram Arkalgud Chandrasetty
Publisher: Academic Press
ISBN: 0128112565
Category : Technology & Engineering
Languages : en
Pages : 192

View

Book Description
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.The reader will learn: - Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation - How to reduce computational complexity and power consumption using computer aided design techniques - All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs - Provides extensive treatment of LDPC decoding algorithms and hardware implementations - Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware - Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis

Author: Yuta Toriyama
Publisher:
ISBN:
Category :
Languages : en
Pages : 133

View

Book Description
Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards, such as wireless communications, wireline communications, and data storage systems. In the pursuit of codes with even higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong replacement candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts. Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency. We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.

Author: Kuo-Lun Huang
Publisher:
ISBN:
Category : Algorithms
Languages : en
Pages : 125

View

Book Description
The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models. We statistically analyze the behavior of stochastic LDPC decoding, including randomization in the stochastic streams and convergence of transition probabilities in iterative decoding process. We also present a space and time-efficient code bit determination method for stochastic LDPC decoders. In addition, we investigate and characterize the decoding errors of stochastic LDPC decoders and as an example, study the stochastic-decoding-specific trapping sets in the (1056,528) LDPC code used in the WiMAX standard. This study helps to develop methods to lower the error floor of stochastic decoding. We propose a reduced-latency stochastic decoding algorithm for LDPC codes. The proposed algorithm, called Conditional Stochastic Decoding (CSD), improves error rate performance and reduces the decoding latency by more than 30% compared with the existing stochastic decoders. We also characterize the performance of CSD in various communication schemes. For example, we show the advantages of using the proposed CSD algorithm in the Automatic Repeat reQuest (ARQ) scheme when compared with other iterative decoding algorithms. We extend our study of stochastic decoding to non-AWGN channel models including the Binary Symmetric Channel (BSC), the Z-channel, and the Rayleigh fading channel. We introduce scaling methods to improve the performance of stochastic decoding on these channel models. On the Rayleigh fading channel, the proposed method not only reduces the computational complexity of the stochastic decoding, but also provides 3-dB improvement in performance and lowers the error floor. Simplicity of hardware implementation, low latency, and good error rate performance of the proposed schemes make them suitable for emerging communication standards.

Author: Zhiqiang Cui
Publisher:
ISBN:
Category : Decoders (Electronics)
Languages : en
Pages : 218

View

Book Description
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g., N>1000 bits), which lead to a linear increase of the size of memory for storing all the soft messages in LDPC decoding. In the next generation communication systems, the target data rates range from a few hundred Mbit/sec to several Gbit/sec. To achieve those very high decoding throughput, a large amount of computation units are required, which will significantly increase the hardware cost and power consumption of LDPC decoders. LDPC codes are decoded using iterative decoding algorithms. The decoding latency and power consumption are linearly proportional to the number of decoding iterations. A decoding approach with fast convergence speed is highly desired in practice. This thesis considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory requirement, low complexity implementation, and high speed decoding of LDPC codes. We propose a memory efficient partially parallel decoder architecture suited for quasi-cyclic LDPC (QC-LDPC) codes using Min-Sum decoding algorithm. We develop an efficient architecture for general permutation matrix based LDPC codes. We have explored various approaches to linearly increase the decoding throughput with a small amount of hardware overhead. We develop a multi-Gbit/sec LDPC decoder architecture for QC-LDPC codes and prototype an enhanced partially parallel decoder architecture for a Euclidian geometry based LDPC code on FPGA. We propose an early stopping scheme and an extended layered decoding method to reduce the number of decoding iterations for undecodable and decodable sequence received from channel. We also propose a low-complexity optimized 2-bit decoding approach which requires comparable implementation complexity to weighted bit flipping based algorithms but has much better decoding performance and faster convergence speed.

Author: Haeng Kon Kim
Publisher: Springer Science & Business Media
ISBN: 9400747861
Category : Technology & Engineering
Languages : en
Pages : 390

View

Book Description
This volume contains thirty revised and extended research articles written by prominent researchers participating in an international conference in engineering technologies and physical science and applications. The conference serves as good platforms for the engineering community to meet with each other and to exchange ideas. The conference has also struck a balance between theoretical and application development. The conference is truly international meeting with a high level of participation from many countries. Topics covered include chemical engineering, circuits, communications systems, control theory, engineering mathematics, systems engineering, manufacture engineering, and industrial applications. The book offers the state of art of tremendous advances in engineering technologies and physical science and applications, and also serves as an excellent reference work for researchers and graduate students working with/on engineering technologies and physical science and applications.

Author: Yang Han
Publisher:
ISBN:
Category :
Languages : en
Pages : 300

View

Book Description
Low-density parity check (LDPC) codes have experienced tremendous popularity due to their capacity-achieving performance. In this dissertation, several different aspects of LDPC coding and its applications to magnetic storage are investigated. One of the most significant issues that impedes the use of LDPC codes in many systems is the error-rate floor phenomenon associated with their iterative decoders. By delineating the fundamental principles, we extend to partial response channels algorithms for predicting the error rate performance in the floor region for the binary-input AWGN channel. We develop three classes of decoding algorithms for mitigating the error floor by directly tackling the cause of the problem: trapping sets. In our experiments, these algorithms provide multiple orders of improvement over conventional decoders at the cost of various implementation complexity increases. Product codes are widely used in magnetic recording systems where errors are both isolated and bursty. A dual-mode decoding technique for Reed-Solomon-code-based product codes is proposed, where the second decoding mode involves maximum-likelihood erasure decoding of the binary images of the Reed-Solomon codewords. By exploring a tape storage application, we demonstrate that this dual-mode decoding system dramatically improves the performance of product codes. Moreover, the complexity added by the second decoding mode is manageable. We also show the performance of this technique on a product code which has an LDPC code in thecolumns. Run-length-limited (RLL) codes are ubiquitous in today's disk drives. Using RLL codes has enabled drive designers to pack data very efficiently onto the platter surface by ensuring stable symbol-timing recovery. We consider a concatenation system design with an LDPC code and an RLL code as components to simultaneously achieve desirable features such as: soft information availability to the LDPC decoder, the preservation of the LDPC code's structure, and the capability of correcting long erasure bursts. We analyze the performance of LDPC-coded magnetic recording channel in the presence of media noise. We employ advanced signal processing for the pattern-dependent-noise-predictive channel detectors, and demonstrate that a gain of over 1 dB or a linear density gain of about 8% relative to a comparable Reed-Solomon is attainable by using an LDPC code.

Author: Tinoosh Mohsenin
Publisher:
ISBN: 9781124509181
Category :
Languages : en
Pages :

View

Book Description
Many emerging and future communication applications require a significant amount of high throughput data processing and operate with decreasing power budgets. This need for greater energy efficiency and improved performance of electronic devices demands a joint optimization of algorithms, architectures, and implementations. Low Density Parity Check (LDPC) decoding has received significant attention due to its superior error correction performance, and has been adopted by recent communication standards such as 10GBASE-T 10 Gigabit Ethernet. Currently high performance LDPC decoders are designed to be dedicated blocks within a System-on-Chip (SoC) and require many processing nodes. These nodes require a large set of interconnect circuitry whose delay and power are wire-dominated circuits. Therefore, low clock rates and increased area are a common result of the codes' inherent irregular and global communication patterns. As the delay and energy costs caused by wires are likely to increase in future fabrication technologies new solutions dealing with future VLSI challenges must be considered. Three novel message-passing decoding algorithms, Split-Row, Multi-Splitand Split-Row Threshold are introduced, which significantly reduce processor logical complexity and local and global interconnections. One conventional and four Split-Row Threshold LDPC decoders compatible with the 10GBASE-T standard are implemented in 65 nm CMOS and presented along with their trade-offs in error correction performance, wire interconnect complexity, decoder area, power dissipation, and speed. For additional power saving, an adaptive wordwidth decoding algorithm is proposed which switches between a 6-bit Normal Mode and a reduced 3-bit Low Power Mode depending on the SNR and decoding iteration. A 16-way Split-Row Threshold with adaptive wordwidth implementation achieves improvements in area, throughput and energy efficiency of 3.9x, 2.6x, and 3.6x respectively, compared to a MinSum Normalized implementation, with an SNR loss of 0.25 dB at BER = 10−7. The decoder occupies a die area of 5.10 mm2, operates up to 185 MHz at 1.3 V, and attains an average throughput of 85.7 Gbps with early-termination. Low power operation at 0.6 V gives a worst case throughput of 9.3 Gbps--above the 6.4 Gbps 10GBASE-T requirement, and an average power of 31 mW.

Author: Pierre-Emmanuel Gaillardon
Publisher: CRC Press
ISBN: 1482262193
Category : Technology & Engineering
Languages : en
Pages : 526

View

Book Description
During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields. Field programmable gate arrays (FPGAs) are one of the most famous architecture families of reconfigurable devices. FPGAs can be seen as arrays of logic units that can be reconfigured to realize any digital systems. Their high versatility has enabled designers to drastically reduce time to market, and made FPGAs suitable for prototyping or small production series in many branches of industrial products. In addition, and thanks to innovations at the architecture level, FPGAs are now conquering segments of mass markets such as mobile communications. Reconfigurable Logic: Architecture, Tools, and Applications offers a snapshot of the state of the art of reconfigurable logic systems. Covering a broad range of architectures, tools, and applications, this book: Explores classical FPGA architectures and their supporting tools Evaluates recent proposals related to FPGA architectures, including the use of network-on-chips (NoCs) Examines reconfigurable processors that merge concepts borrowed from the reconfigurable domain into processor design Exploits FPGAs for high-performance systems, efficient error correction codes, and high-bandwidth network routers with built-in security Expounds on emerging technologies to enhance FPGA architectures, improve routing structures, and create non-volatile configuration flip-flops Reconfigurable Logic: Architecture, Tools, and Applications reviews current trends in reconfigurable platforms, providing valuable insight into the future potential of reconfigurable systems.

Author:
Publisher: Academic Press
ISBN: 012397223X
Category : Technology & Engineering
Languages : en
Pages : 687

View

Book Description
This book gives a review of the principles, methods and techniques of important and emerging research topics and technologies in Channel Coding, including theory, algorithms, and applications. Edited by leading people in the field who, through their reputation, have been able to commission experts to write on a particular topic. With this reference source you will: - Quickly grasp a new area of research - Understand the underlying principles of a topic and its applications - Ascertain how a topic relates to other areas and learn of the research issues yet to be resolved - Quick tutorial reviews of important and emerging topics of research in Channel Coding - Presents core principles in Channel Coding theory and shows their applications - Reference content on core principles, technologies, algorithms and applications - Comprehensive references to journal articles and other literature on which to build further, more specific and detailed knowledge