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Design for Yield Enhancement and Reconfiguration in Large Area VLSI/WSI Architectures

Author: Sy-Yen Kuo
Publisher:
ISBN:
Category :
Languages : en
Pages : 194

Book Description

Wafer Scale Integration

Author: Earl E. Swartzlander Jr.
Publisher: Springer Science & Business Media
ISBN: 1461316219
Category : Technology & Engineering
Languages : en
Pages : 515

Book Description
Wafer Scale Integration (WSI) is the culmination of the quest for larger integrated circuits. In VLSI chips are developed by fabricating a wafer with hundreds of identical circuits, testing the circuits, dicing the wafer, and packaging the good dice. In contrast in WSI, a wafer is fabricated with several types of circuits (generally referred to as cells), with multiple instances of each cell type, the cells are tested, and good cells are interconnected to realize a system on the wafer. Since most signal lines stay on the wafer, stray capacitance is low, so that high speeds are achieved with low power consumption. For the same technology a WSI implementation may be a factor of five faster, dissipate a factor of ten less power, and require one hundredth to one thousandth the volume. Successful development of WSI involves many overlapping disciplines, ranging from architecture to test design to fabrication (including laser linking and cutting, multiple levels of interconnection, and packaging). This book concentrates on the areas that are unique to WSI and that are as a result not well covered by any of the many books on VLSI design. A unique aspect of WSI is that the finished circuits are so large that there will be defects in some portions of the circuit. Accordingly much attention must be devoted to designing architectures that facilitate fault detection and reconfiguration to of WSI include fabrication circumvent the faults. Other unique aspects technology and packaging.

Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multi-Precessor Systems

Author: Israel Koren
Publisher:
ISBN:
Category :
Languages : en
Pages : 52

Book Description
New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emergent area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance, and yield improvement techniques. Fault-tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault-tolerance at work in these multi-processor systems. These precepts are useful to then present certain techniques that will incorporate fault-tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques. (Author).

Design for Yield Enhancement and Reconfiguration in Large Area VLSI/WSI Architectures

Wafer Scale Integration

Yield and Performance Enhancement Through Redundancy in VLSI and WSI Multi-Precessor Systems

Manufacturing Yield Evaluation of VLSI/WSI Systems

The Summary of Engineering Research

American Doctoral Dissertations

The Summary of Engineering Research

Dissertation Abstracts International

Fault Diagnosis and Yield Enhancement in Defect Tolerant VLSI/WSI Parallel Architectures

1991 Proceedings