Construction of Structured Low-density Parity-check Codes PDF Download

Author: Lei Chen
Publisher:
ISBN:
Category :
Languages : en
Pages : 340

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Author: Gabofetswe Alafang Malema
Publisher:
ISBN:
Category : Coding theory
Languages : en
Pages : 160

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Book Description
The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. Two main methods for constructing structured codes are introduced. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. The outcome of this study is a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.

Author: Vikram Arkalgud Chandrasetty
Publisher: Academic Press
ISBN: 0128112565
Category : Technology & Engineering
Languages : en
Pages : 192

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Book Description
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.The reader will learn: - Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation - How to reduce computational complexity and power consumption using computer aided design techniques - All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs - Provides extensive treatment of LDPC decoding algorithms and hardware implementations - Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware - Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis

Author: Martin Tomlinson
Publisher: Springer
ISBN: 3319511033
Category : Technology & Engineering
Languages : en
Pages : 527

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Book Description
This book discusses both the theory and practical applications of self-correcting data, commonly known as error-correcting codes. The applications included demonstrate the importance of these codes in a wide range of everyday technologies, from smartphones to secure communications and transactions. Written in a readily understandable style, the book presents the authors’ twenty-five years of research organized into five parts: Part I is concerned with the theoretical performance attainable by using error correcting codes to achieve communications efficiency in digital communications systems. Part II explores the construction of error-correcting codes and explains the different families of codes and how they are designed. Techniques are described for producing the very best codes. Part III addresses the analysis of low-density parity-check (LDPC) codes, primarily to calculate their stopping sets and low-weight codeword spectrum which determines the performance of th ese codes. Part IV deals with decoders designed to realize optimum performance. Part V describes applications which include combined error correction and detection, public key cryptography using Goppa codes, correcting errors in passwords and watermarking. This book is a valuable resource for anyone interested in error-correcting codes and their applications, ranging from non-experts to professionals at the forefront of research in their field. This book is open access under a CC BY 4.0 license.

Author:
Publisher:
ISBN:
Category : Electronic books
Languages : en
Pages : 82

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Low Density Parity-Check, or LDPC, codes have been a popular error correction choice in the recent years. Its use of soft-decision decoding through a message-passing algorithm and its channel-capacity approaching performance has made LDPC codes a strong alternative to that of Turbo codes. However, its disadvantages, such as encoding complexity, discourages designers from implementing these codes. This thesis will present a type of error correction code which can be considered as a subset of LDPC codes. These codes are called Repeat-Accumulate codes and are named such because of their encoder structure. These codes is seen as a type of LDPC codes that has a simple encoding method similar to Turbo codes. What makes these codes special is that they can have a simple encoding process and work well with a soft-decision decoder. At the same time, RA codes have been proven to be codes that will work well at short to medium lengths if they are systematic. Therefore, this thesis will argue that LDPC codes can avoid some of its encoding disadvantage by becoming LDPC codes with systematic RA codes. This thesis will also show in detail how RA codes are good LDPC codes by comparing its bit error performance against other LDPC simulation results tested at short to medium code lengths and with different LDPC parity-check matrix constructions. With an RA parity-check matrix describing our LDPC code, we will see how changing the interleaver structure from a random construction to that of a structured can lead to improved performance. Therefore, this thesis will experiment using three different types of interleavers which still maintain the simplicity of encoding complexity of the encoder but at the same time show potential improvement of bit error performance compared to what has been previously seen with regular LDPC codes.

Author: Juane Li
Publisher: Cambridge University Press
ISBN: 1107175682
Category : Computers
Languages : en
Pages : 259

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In this book, leading authorities unify algebraic- and graph-based LDPC code designs and constructions into a single theoretical framework.

Author: Jaehong Kim
Publisher:
ISBN:
Category : Algorithms
Languages : en
Pages :

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The main objective of our research is to design practical low-density parity-check (LDPC) codes which provide a wide range of code rates in a rate-compatible fashion. To this end, we first propose a rate-compatible puncturing algorithm for LDPC codes at short block lengths (up to several thousand symbols). The proposed algorithm is based on the claim that a punctured LDPC code with a smaller level of recoverability has better performance. The proposed algorithm is verified by comparing performance of intentionally punctured LDPC codes (using the proposed algorithm) with randomly punctured LDPC codes. The intentionally punctured LDPC codes show better bit error rate (BER) performances at practically short block lengths. Even though the proposed puncturing algorithm shows excellent performance, several problems are still remained for our research objective. First, how to design an LDPC code of which structure is well suited for the puncturing algorithm. Second, how to provide a wide range of rates since there is a puncturing limitation with the proposed puncturing algorithm. To attack these problems, we propose a new class of LDPC codes, called efficiently-encodable rate-compatible (E2RC) codes, in which the proposed puncturing algorithm concept is imbedded. The E2RC codes have several strong points. First, the codes can be efficiently encoded. We present low-complexity encoder implementation with shift-register circuits. In addition, we show that a simple erasure decoder can also be used for the linear-time encoding of these codes. Thus, we can share a message-passing decoder for both encoding and decoding in transceiver systems that require an encoder/decoder pair. Second, we show that the non-systematic parts of the parity-check matrix are cycle-free, which ensures good code characteristics. Finally, the E2RC codes having a systematic rate-compatible puncturing structure show better puncturing performance than any other LDPC codes in all ranges of code rates.

Author:
Publisher:
ISBN:
Category :
Languages : en
Pages :

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In this doctoral dissertation, a construction of binary and nonbinary low-density parity-check (LDPC) codes with quasi-cyclic (QC) structures is presented. First, a general construction of RC-constrained arrays of circulant permutation matrices is introduced, then a specific construction method based on additive subgroups of finite fields is presented. Array masking is also proposed to improve the waterfall-region performance of the QC-LDPC codes, where an algorithm to construct irregular masking matrices is introduced for low error floors. Simulations show that all the above-constructed codes perform well on AWGN channels. Also presented in this dissertation is an LDPC-based error control scheme in a multicast network where a well-known network coding is used. With this scheme, error performance of the system can be improved and equal error protection can be achieved. Finally, an iterative decoding with backtracking is presented. This decoding algorithm greatly lowers the error floors of many regular and irregular LDPC codes of different constructions, and in many cases can push the error floors down to a level limited by the codes' minimum distances. Performance analysis and error floor estimation for the proposed algorithm are also performed.

Author: Xudong Ma
Publisher:
ISBN: 9780494433096
Category :
Languages : en
Pages : 125

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This thesis focuses on designing Low-Density Parity-Check (LDPC) codes for forward-error-correction. The target application is real-time multimedia communications over packet networks. We investigate two code design issues, which are important in the target application scenarios, designing LDPC codes with low decoding latency, and constructing capacity-approaching LDPC codes with very low error probabilities. On designing LDPC codes with low decoding latency, we present a framework for optimizing the code parameters so that the decoding can be fulfilled after only a small number of iterative decoding iterations. The brute force approach for such optimization is numerical intractable, because it involves a difficult discrete optimization programming. In this thesis, we show an asymptotic approximation to the number of decoding iterations. Based on this asymptotic approximation, we propose an approximate optimization framework for finding near-optimal code parameters, so that the number of decoding iterations is minimized. The approximate optimization approach is numerically tractable. Numerical results confirm that the proposed optimization approach has excellent numerical properties, and codes with excellent performance in terms of number of decoding iterations can be obtained. Our results show that the numbers of decoding iterations of the codes by the proposed design approach can be as small as one-fifth of the numbers of decoding iterations of some previously well-known codes. The numerical results also show that the proposed asymptotic approximation is generally tight for even non-extremely limiting cases. On constructing capacity-approaching LDPC codes with very low error probabilities, we propose a new LDPC code construction scheme based on 2-lifts. Based on stopping set distribution analysis, we propose design criteria for the resulting codes to have very low error floors. High error floors are the main problems of previously constructed capacity-approaching codes, which prevent them from achieving very low error probabilities. Numerical results confirm that codes with very low error floors can be obtained by the proposed code construction scheme and the design criteria. Compared with the codes by the previous standard construction schemes, which have error floors at the levels of 10−3 to 10−4, the codes by the proposed approach do not have observable error floors at the levels higher than 10−7. The error floors of the codes by the proposed approach are also significantly lower compared with the codes by the previous approaches to constructing codes with low error floors.

Author: Lizhi Wu
Publisher:
ISBN:
Category : Coding theory
Languages : en
Pages : 0

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With the rapid expansion of communication networks, there has been an increasing demand for efficient and reliable digital data transmission and storage systems. Many efficient codes have been developed. The LDPC code is one of them. In this thesis, the sum-product algorithm is used in the decoding of LDPC codes. Some schemes for encoding LDPC codes have been studied. In particular, two methods of producing regular H matrices have been attempted that include short cycles of length four with code rates of 0.5, and we present three schemes of finding regular H matrices which do not include short cycles of length four with code rate being 0.5. The effect of short cycles in the bipartite graph of regular LDPC codes has been considered. The simulation results show that the BER performances of regular H matrices that do not include short cycles of length four based on BPSK or 8PSK on AWGN channel is better than those of regular H matrices that include short cycles of length four. In conclusion, in order to obtain good performance with LDPC code, one should design H matrix related to bipartite graph without short cycles.