Author: Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
Charge Pump Design in Low-voltage CMOS Technology
Author: PMOS-based Integrated Charge Pumps with Extended Voltage Range in Standard CMOS Technology
Author: Jingqi LiuCharge Pump Circuit Design
Author: Feng PanPublisher: McGraw Hill Professional
ISBN: 0071491422
Category : Technology & Engineering
Languages : en
Pages : 264
Book Description
Charge pumps are finding increased attention and diversified usage in the new era of nanometer-generation chips used in different systems. This book explains the different architectures and requirements for an efficient charge pump design and explains each step in detail. It's filled with extra hands-on design information, potential pitfalls to avoid, and practical ideas harnessed from the authors' extensive experience designing charge pumps.
Low-Power Digital VLSI Design
Author: Abdellatif BellaouarPublisher: Springer Science & Business Media
ISBN: 1461523559
Category : Technology & Engineering
Languages : en
Pages : 539
Book Description
Low-Power Digital VLSI Design: Circuits and Systems addresses both process technologies and device modeling. Power dissipation in CMOS circuits, several practical circuit examples, and low-power techniques are discussed. Low-voltage issues for digital CMOS and BiCMOS circuits are emphasized. The book also provides an extensive study of advanced CMOS subsystem design. A low-power design methodology is presented with various power minimization techniques at the circuit, logic, architecture and algorithm levels. Features: Low-voltage CMOS device modeling, technology files, design rules Switching activity concept, low-power guidelines to engineering practice Pass-transistor logic families Power dissipation of I/O circuits Multi- and low-VT CMOS logic, static power reduction circuit techniques State of the art design of low-voltage BiCMOS and CMOS circuits Low-power techniques in CMOS SRAMS and DRAMS Low-power on-chip voltage down converter design Numerous advanced CMOS subsystems (e.g. adders, multipliers, data path, memories, regular structures, phase-locked loops) with several design options trading power, delay and area Low-power design methodology, power estimation techniques Power reduction techniques at the logic, architecture and algorithm levels More than 190 circuits explained at the transistor level.
Low Power RF Circuit Design in Standard CMOS Technology
Author: Unai AlvaradoPublisher: Springer Science & Business Media
ISBN: 3642229875
Category : Technology & Engineering
Languages : en
Pages : 248
Book Description
Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.
Area Efficiency Improvement of CMOS Charge Pump Circuits
Author: Ryan PerignyPublisher:
ISBN:
Category : Charge transfer devices (Electronics)
Languages : en
Pages : 124
Book Description
In this thesis, the literature relating to charge pump dc-dc converters and their uses is reviewed. Charge pumps are useful in many circuits, including low-voltage circuits, dynamic random access memory circuits, switched-capacitor circuits, EEPROM's and transceivers. The important issues relating to charge pump design are power efficiency, output voltage ripple and area efficiency. This thesis describes the operation of three types of charge pump circuits. Power efficiency theory of charge pumps is discussed in detail. A method of estimating the output ripple of a charge pump from the size of the capacitors used is described. The optimal distribution of available capacitance for minimizing output ripple or maximizing power efficiency is derived. The tradeoffs between output ripple, power efficiency and total capacitance are discussed. The considerations involved in the design of charge pump circuits are described. A new charge pump circuit that uses two cascoded buffer transistors to improve the area efficiency is proposed. An implementation consisting of one of each of the three types of charge pumps was simulated for a 0.35-micron CMOS process. The simulation results verify the improved area efficiency of the double cascode charge pump.
CMOS Circuits for Electromagnetic Vibration Transducers
Author: Dominic MaurathPublisher: Springer
ISBN: 9401792720
Category : Technology & Engineering
Languages : en
Pages : 309
Book Description
Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100μW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over 4.1V. - Two special chapters on analog circuit design – it studies benefits and obstacles on implemented chip prototypes with three goals: ultra- low power, wide supply voltage range, and integration with standard technologies. Alternative design approaches are pursued using bulk-input transistor stages in forward-bias operation for amplifiers, modulators, and references. - Comprehensive Appendix – with additional fundamental analysis, design and scaling guidelines, circuit implementation tables and dimensions, schematics, source code listings, bill of material, etc. The discussed prototypes and given design guidelines are tested with real vibration transducer devices. The intended readership is graduate students in advanced courses, academics and lecturers, R&D engineers.
Low-Voltage CMOS Log Companding Analog Design
Author: Francisco Serra-GraellsPublisher: Springer Science & Business Media
ISBN: 0306487217
Category : Technology & Engineering
Languages : en
Pages : 209
Book Description
Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.
High-Performance Integrated Charge Pumps
Author: Andrea BalloPublisher: Springer Nature
ISBN: 3031435974
Category : Technology & Engineering
Languages : en
Pages : 171
Book Description
This book enables readers to gain a deep understanding of the challenges related to the design of a charge pump (CP). Analysis, modeling, design strategies and topologies are treated in detail. Novel and high-performance CP topologies and related design are organized in a coherent manner, with particular care devoted to ultra-low power and energy harvesting applications. The authors provide basic theoretical foundations as needed, in order to set the stage for readers’ comprehension of analyses and results. Exhaustive methodologies are presented and analytical derivations are included, enabling readers to gain insight on the main dependencies among the relevant circuit parameters. Although the material is presented in a formal and theoretical manner, emphasis is on the design perspective, using many practical examples and measured results.
A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices
Author: Jordi Colomer-FarraronsPublisher: Springer Science & Business Media
ISBN: 9400706863
Category : Technology & Engineering
Languages : en
Pages : 169
Book Description
A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc... that are detected through a three-electrodes amperometric BioSensor approach. The device is envisaged as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the skin. The sensor is controlled with a Potentiostat circuit and then, a post-processing unit detects the desired levels and activates the transmission via a backscattering method by the inductive link. All the instrumentation, except the power module, is implemented in the so called BioChip. Following the idea of the powering link to harvest energy of the magnetic induced link at the implanted device, a Multi-Harvesting Power Chip (MHPC) has been also designed.