Author: Alexandru CiobanuPublisher:
ISBN: 9780494841617
Category :
Languages : en
Pages :
Book Description
Adaptive Multiset Stochastic Decoding of Non-binary LDPC Codes
Author: Alexandru CiobanuPublisher:
ISBN: 9780494841617
Category :
Languages : en
Pages :
Book Description
Area-efficient Stochastic Decoder Architectures for Non-binary LDPC Codes
Author: Stochastic Decoding of LDPC Codes Over GF(q)
Author: Gabi SarkisNon-Binary Error Control Coding for Wireless Communication and Data Storage
Author: Rolando Antonio CarrascoPublisher: John Wiley & Sons
ISBN: 047074040X
Category : Technology & Engineering
Languages : en
Pages : 322
Book Description
Comprehensive introduction to non-binary error-correction coding techniques Non-Binary Error Control Coding for Wireless Communication and Data Storage explores non-binary coding schemes that have been developed to provide an alternative to the Reed – Solomon codes, which are expected to become unsuitable for use in future data storage and communication devices as the demand for higher data rates increases. This book will look at the other significant non-binary coding schemes, including non-binary block and ring trellis-coded modulation (TCM) codes that perform well in fading conditions without any expansion in bandwidth use, and algebraic-geometric codes which are an extension of Reed-Solomon codes but with better parameters. Key Features: Comprehensive and self-contained reference to non-binary error control coding starting from binary codes and progressing up to the latest non-binary codes Explains the design and construction of good non-binary codes with descriptions of efficient non-binary decoding algorithms with applications for wireless communication and high-density data storage Discusses the application to specific cellular and wireless channels, and also magnetic storage channels that model the reading of data from the magnetic disc of a hard drive. Includes detailed worked examples for each coding scheme to supplement the concepts described in this book Focuses on the encoding, decoding and performance of both block and convolutional non-binary codes, and covers the Kötter-Vardy algorithm and Non-binary LDPC codes This book will be an excellent reference for researchers in the wireless communication and data storage communities, as well as development/research engineers in telecoms and storage companies. Postgraduate students in these fields will also find this book of interest.
Iterative Linear Programming Decoding of Non-binary LDPC Codes with Linear Complexity
Author: Dina GoldinPublisher:
ISBN:
Category : Decoders (Electronics)
Languages : en
Pages : 60
Book Description
Low Complexity Decoding of Non-binary LDPC Codes Over AWGN Channels
Author: Pia Aviva ZobelPublisher:
ISBN:
Category : Decoders (Electronics)
Languages : en
Pages : 80
Book Description
A Class of Non-binary LDPC Codes
Author: Deepak GilraPublisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
In this thesis we study Low Density Parity Check (LDPC) and LDPC like codes over non-binary fields. We extend the concepts used for non-binary LDPC codes to generalize Product Accumulate (PA) codes to non-binary fields. We present simulation results that show that PA codes over GF(4) performs considerably better than binary PA codes at smaller block lengths and slightly better at large block lengths. We also propose a trellis based decoding algorithm to decode PA codes and show that its complexity is considerably lower than the message-passing algorithm. In the second part of the thesis we study the convergence properties of non-binary PA codes and non-binary LDPC codes. We use EXIT-charts to study the convergence properties of non-binary LDPC codes with different mean column weights and show why certain irregularities are better. Although the convergence threshold predicted by EXIT-charts on non-binary LDPC codes is quite optimistic we can still use EXIT-charts for comparison between non-binary LDPC codes with different mean column weights.
Algebraic Constructions of High Performance and Efficiently Encodable Non-binary Quasi-cyclic LDPC Codes
Author: Bo ZhouLow-complexity Decoding Algorithms and Architectures for Non-binary LDPC Codes
Author: Fang CaiPublisher:
ISBN:
Category :
Languages : en
Pages : 149
Book Description
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this thesis, three decoding algorithms and corresponding VLSI architectures are proposed for NB-LDPC codes to lower the computational complexity and memory requirement. The first design is based on the proposed relaxed Min-max decoding algorithm. A novel relaxed check node processing scheme is proposed for the Min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p̂) can be uniquely represented by a linear combination of $p$ independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25̂) can achieve 52% higher efficiency in terms of throughput-over-area ratio. The second design is based on a proposed enhanced iterative hard reliability-based majority-logic decoding. The recently developed iterative hard reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. Novel schemes are proposed for the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E- )IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Many existing NB-LDPC code construction methods lead to quasi-cyclic or cyclic codes. Both types of codes are considered in our design. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous designs based on the Min-max decoding algorithm, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss. The third design is based on a proposed check node decoding scheme using power representation of finite field elements. Novel schemes are proposed for the Min-max check node processing by making use of the cyclical-shift property of the power representation of finite field elements. Compared to previous designs based on the Min-max algorithm with forward-backward scheme, the proposed check node units (CNUs) do not need the complex switching network. Moreover, the multiplications of the parity check matrix entries are efficiently incorporated. For a Min-max NB-LDPC decoder over GF(32), the proposed scheme reduces the CNU area by at least 32%, and leads to higher clock frequency.
Efficient Algorithms for Stochastic Decoding of LDPC Codes
Author: Kuo-Lun HuangPublisher:
ISBN:
Category : Algorithms
Languages : en
Pages : 125
Book Description
The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models. We statistically analyze the behavior of stochastic LDPC decoding, including randomization in the stochastic streams and convergence of transition probabilities in iterative decoding process. We also present a space and time-efficient code bit determination method for stochastic LDPC decoders. In addition, we investigate and characterize the decoding errors of stochastic LDPC decoders and as an example, study the stochastic-decoding-specific trapping sets in the (1056,528) LDPC code used in the WiMAX standard. This study helps to develop methods to lower the error floor of stochastic decoding. We propose a reduced-latency stochastic decoding algorithm for LDPC codes. The proposed algorithm, called Conditional Stochastic Decoding (CSD), improves error rate performance and reduces the decoding latency by more than 30% compared with the existing stochastic decoders. We also characterize the performance of CSD in various communication schemes. For example, we show the advantages of using the proposed CSD algorithm in the Automatic Repeat reQuest (ARQ) scheme when compared with other iterative decoding algorithms. We extend our study of stochastic decoding to non-AWGN channel models including the Binary Symmetric Channel (BSC), the Z-channel, and the Rayleigh fading channel. We introduce scaling methods to improve the performance of stochastic decoding on these channel models. On the Rayleigh fading channel, the proposed method not only reduces the computational complexity of the stochastic decoding, but also provides 3-dB improvement in performance and lowers the error floor. Simplicity of hardware implementation, low latency, and good error rate performance of the proposed schemes make them suitable for emerging communication standards.