Author: Zheming LiPublisher:
ISBN:
Category :
Languages : en
Pages : 144
Book Description
A General Physical Model for Double-gate SOI MOSFETs
Author: Zheming LiPlanar Double-Gate Transistor
Author: Amara AmaraPublisher: Springer Science & Business Media
ISBN: 1402093411
Category : Technology & Engineering
Languages : en
Pages : 215
Book Description
Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each dif?culty has found a solution.
Modeling Independent-double-gate Silicon-on-insulator (IDG SOI) MOSFET
Author: Sudheer VootkuriPublisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 168
Book Description
Silicon-On-Insulator (SOI) Technology
Author: O. KononchukPublisher: Elsevier
ISBN: 0857099256
Category : Technology & Engineering
Languages : en
Pages : 503
Book Description
Silicon-On-Insulator (SOI) Technology: Manufacture and Applications covers SOI transistors and circuits, manufacture, and reliability. The book also looks at applications such as memory, power devices, and photonics. The book is divided into two parts; part one covers SOI materials and manufacture, while part two covers SOI devices and applications. The book begins with chapters that introduce techniques for manufacturing SOI wafer technology, the electrical properties of advanced SOI materials, and modeling short-channel SOI semiconductor transistors. Both partially depleted and fully depleted SOI technologies are considered. Chapters 6 and 7 concern junctionless and fin-on-oxide field effect transistors. The challenges of variability and electrostatic discharge in CMOS devices are also addressed. Part two covers recent and established technologies. These include SOI transistors for radio frequency applications, SOI CMOS circuits for ultralow-power applications, and improving device performance by using 3D integration of SOI integrated circuits. Finally, chapters 13 and 14 consider SOI technology for photonic integrated circuits and for micro-electromechanical systems and nano-electromechanical sensors. The extensive coverage provided by Silicon-On-Insulator (SOI) Technology makes the book a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics. It is also important for electrical engineers in the automotive and consumer electronics sectors. - Covers SOI transistors and circuits, as well as manufacturing processes and reliability - Looks at applications such as memory, power devices, and photonics
Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs
Author: Jerry G. FossumPublisher: Cambridge University Press
ISBN: 1107030412
Category : Technology & Engineering
Languages : en
Pages : 227
Book Description
Understand the theory, design and applications of FD/SOI MOSFETs and 3-D FinFETs with this concise and clear guide to FD/UTB transistors. Topics covered include short-channel effects, quantum-mechanical effects, applications of UTB devices to floating-body DRAM and conventional SRAM, and nanoscale UTB CMOS performances.
Physical Analysis, Modeling, and Design of Nanoscale Double-gate MOSFETs with Gate-source/drain Underlap
Author: Murshed M. ChowdhuryPublisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
The viability of gate-source/drain underlap as a design parameter, in addition to typical device design parameters like gate length, fin thickness, etc., is investigated in terms of the sensitivity of FinFET performance to the variations of process parameters that influence underlap properties; numerical simulators with UFDG aid this investigation. It is found that while variation in the performance of inverter-based circuits, like the ring oscillator, is reasonable, stability of static random access memory (SRAM) shows wide variation in performance for shorter underlap lengths. Finally, a physics-based compact model for gate tunneling current in DG MOSFETs is developed, verified, and implemented in UFDG to enable reliable prediction of static power consumption in nanoscale FinFET circuits. Model predictions corroborate earlier results that for thinner oxides, present-day silicon oxynitride has to be replaced with high-k dielectrics to control static leakage. However, use of underlap can relax the oxide thickness requirement and hence delay the introduction of high-k dielectrics in FinFET technology.
Frontiers In Electronics: Advanced Modeling Of Nanoscale Electron Devices
Author: Benjamin IniguezPublisher: World Scientific
ISBN: 9814583200
Category : Technology & Engineering
Languages : en
Pages : 204
Book Description
This book consists of four chapters to address at different modeling levels for different nanoscale MOS structures (Single- and Multi-Gate MOSFETs). The collection of these chapters in the book are attempted to provide a comprehensive coverage on the different levels of electrostatics and transport modeling for these devices, and relationships between them. In particular, the issue of quantum transport approaches, analytical predictive 2D/3D modeling and design-oriented compact modeling. It should be of interests to researchers working on modeling at any level, to provide them with a clear explanation of theapproaches used and the links with modeling techniques for either higher or lower levels.
Nanometer CMOS
Author: Juin J. LiouPublisher: CRC Press
ISBN: 1466511702
Category : Science
Languages : en
Pages : 268
Book Description
This book presents the material necessary for understanding the physics, operation, design, and performance of modern MOSFETs with nanometer dimensions. It offers a brief introduction to the field and a thorough overview of MOSFET physics, detailing the relevant basics. The authors apply presented models to calculate and demonstrate transistor characteristics, and they include required input data (e.g., dimensions, doping) enabling readers to repeat the calculations and compare their results. The book introduces conventional and novel advanced MOSFET concepts, such as multiple-gate structures or alternative channel materials. Other topics covered include high-k dielectrics and mobility enhancement techniques, MOSFETs for RF (radio frequency) applications, MOSFET fabrication technology.
Design and Modeling of Non-classical MOSFETs
Author: Bo YuPublisher:
ISBN:
Category :
Languages : en
Pages : 163
Book Description
As bulk CMOS scaling is approaching the limit that is imposed by gate oxide tunneling, body doping, band-to-band tunneling, etc., non-classical MOSFET is becoming an intense subject of very large-scale integration (VLSI) research. Among a variety of non-classical MOSFETs, multiple-gate (MG) MOSFETs which are still based on Si have been proposed to scale down CMOS technology more aggressively because of better control of short-channel effects (SCEs), whereas novel MOSFETs utilizing III-V materials instead of Si are suggested to achieve CMOS performance breakthrough even without scaling down too aggressively due to the large mobility of mobile carriers. This dissertation focuses on the design and modeling of these two categories of non-classical MOSFETs. Actually, many different types of Si-based MG MOSFETs have been designed and even fabricated in the last two decades, including double-gate (DG) MOSFETs, surrounding-gate (SG) MOSFETs, quadruple-gate (QG) MOSFETs, triple-gate (TG) MOSFETs, Pi-gate MOSFETs, Omega-gate MOSFETs, and so on. Although the design work has been pretty much done, specific compact models for these MG MOSFETs other than BSIM, PSP, and HiSIM are in urgent need, because the charge sheet approximation is no longer appropriate for MG MOSFETs due to the so-called "volume inversion" effect. In this dissertation, we will first introduce the complete non-charge-sheet based analytic models of drain current, terminal charges and capacitance coefficients for long channel symmetric DG and SG MOSFETs. The DG and SG models will be generalized to a unified analytic drain current model for all kinds of MG MOSFETs, with some non-trivial yet reasonable approximations. Efforts will also be focused on making the physics-based model more versatile and computationally efficient. On the contrary, the research on III-V MOSFETs is still in the primary phase. Compact modeling for III-V MOSFETs is not being considered in the current stage because the device technology itself is far away from maturity, and the interest of this dissertation is in device design and basic physical modeling. With SCEs treated as the top-drawer consideration, a baseline device design of III-V MOSFET for sub-22nm scaling is proposed based on the thin-BOX-SOI-like structure. Physical modeling of capacitances in III-V MOSFETs has also been carried out to gain a more clear picture of capacitance degradation due to small density-of-states (DOS).
Compact Modeling of Double-Gate MOSFETs
Author: Huaxin LuPublisher:
ISBN:
Category :
Languages : en
Pages : 143
Book Description
Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects. Currently, much research effort is devoted to the development of DG MOSFETs. This dissertation focuses on the compact modeling of DG MOSFETs, aiming to extract the physics of DG MOSFETs and provide a tool for simulating DG MOSFET circuits. We start from the basic Poisson's equation and current continuity equation to rigorously derive the long-channel drain current model without the charge sheet approximation. The model is based on an analytical solution to the potential distribution at any point in the DG MOSFET. It employs one single equation to cover all the operation regions: linear, saturation, and subthreshold, continuously with no fitting parameter. Volume inversion, a non-charge-sheet phenomenon in symmetric DG MOSFETs, is accurately captured by the model. For AC and transient simulations, analytical charge and capacitance models are developed. Both symmetric and asymmetric DG MOSFET models are verified by extensive two dimensional numerical simulations. For small-geometry devices, compact models of the physical phenomena such as short channel effects are developed. In the development of the compact models, special attention is paid to ensure the model is symmetric and continuous in all the operation regions. Quantum effect is also incorporated in the long channel core model. As body doping may be needed to adjust the threshold voltage, we also studied the body doping effect on DG MOSFET and concluded that lightly doped DG MOSFETs can be modeled by adding a threshold voltage shift to the undoped DG MOSFET model. The model has been implemented into SPICE3 and Verilog-A platforms so that it can be used by circuit designers. In the implementation, Newton method is used for solving an implicit equation in the calculation of drain current. We also calibrated the model with respect to the published hardware data to affirm its consistency with the experimental I-V curves. Finally, the model has been released in public domain http://taur.ucsd.edu/~hlu for circuit simulation.