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Author: Marghoob Mohiyuddin Publisher: ISBN: Category : Languages : en Pages : 82
Book Description
Error correcting codes are widely used in digital communication and storage applications. Traditionally, codec implementation complexity has been measured with a software implementation in mind. We address the VLSI implementation issues for the design of a class of error correcting codes - Low Density Parity Check Codes (LDPCs). Keeping hardware implementation issues in mind, we propose a heuristic algorithm to design an LDPC code. We also motivate the case for multi-rate LDPC coding/decoding and propose a reconfigurable VLSI architecture for multirate LDPC decoders. In addition, we describe a heuristic algorithm that computes an effective LDPC code of any given rate which by construction can be implemented on our reconfigurable LDPC decoder
Author: Marghoob Mohiyuddin Publisher: ISBN: Category : Languages : en Pages : 82
Book Description
Error correcting codes are widely used in digital communication and storage applications. Traditionally, codec implementation complexity has been measured with a software implementation in mind. We address the VLSI implementation issues for the design of a class of error correcting codes - Low Density Parity Check Codes (LDPCs). Keeping hardware implementation issues in mind, we propose a heuristic algorithm to design an LDPC code. We also motivate the case for multi-rate LDPC coding/decoding and propose a reconfigurable VLSI architecture for multirate LDPC decoders. In addition, we describe a heuristic algorithm that computes an effective LDPC code of any given rate which by construction can be implemented on our reconfigurable LDPC decoder
Author: Xinmiao Zhang Publisher: CRC Press ISBN: 1351831224 Category : Technology & Engineering Languages : en Pages : 387
Book Description
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.
Author: Xiaohua Tian Publisher: Springer Science & Business Media ISBN: 3642147038 Category : Technology & Engineering Languages : en Pages : 193
Book Description
This book presents a collection of algorithms and VLSI architectures of entropy (or statistical) codecs of recent video compression standards, with focus on the H.264/AVC standard. For any visual data compression scheme, there exists a combination of two, or all of the following three stages: spatial, temporal, and statistical compression. General readers are first introduced with the various algorithms of the statistical coders. The VLSI implementations are also reviewed and discussed. Readers with limited hardware design background are also introduced with a design methodology starting from performance-complexity analyses to software/hardware co-simulation. A typical design of the Contextbased Adaptive Binary Arithmetic Coding (CABAC) encoder is also presented in details. To support System-on-Chip design environment, the CABAC design is wrapped with a SoC-based Wishbone system bus interface.
Author: Sabih H. Gerez Publisher: John Wiley & Sons ISBN: 0471984892 Category : Computers Languages : en Pages : 356
Book Description
Modern microprocessors such as Intel's Pentium chip typically contain many millions of transistors. They are known generically as Very Large-Scale Integrated (VLSI) systems, and their sheer scale and complexity has necessitated the development of CAD tools to automate their design. This book focuses on the algorithms which are the building blocks of the design automation software which generates the layout of VLSI circuits. Courses on this area are typically elective courses taken at senior undergrad or graduate level by students of Electrical and Electronic Engineering, and sometimes in Computer Science, or Computer Engineering.
Author: Ahmad Darabiha Publisher: ISBN: 9780494398173 Category : Languages : en Pages : 228
Book Description
Near-capacity performance and parallelizable decoding algorithms have made Low-Density Parity Check (LDPC) codes a powerful competitor to previous generations of codes, such as Turbo and Reed Solomon codes, for reliable high-speed digital communications. As a result, they have been adopted in several emerging standards. This thesis investigates VLSI architectures for multi-Gbps power and area-efficient LDPC decoders. To reduce the node-to-node communication complexity, a decoding scheme is proposed in which messages are transferred and computed bit-serially. Also, a broadcasting scheme is proposed in which the traditional computations required in the sum-product and min-sum decoding algorithms are repartitioned between the check and variable node units. To increase decoding throughput, a block interlacing scheme is investigated which is particularly advantageous in fully-parallel LDPC decoders. To increase decoder energy efficiency, an efficient early termination scheme is proposed. In addition, an analysis is given of how increased hardware parallelism coupled with a reduced supply voltage is a particularly effective approach to reduce the power consumption of LDPC decoders. These architectures and circuits are demonstrated in two hardware implementations. Specifically, a 610-Mbps bit-serial fully-parallel (480, 355) LDPC decoder on a single Altera Stratix EP1S80 device is presented. To our knowledge, this is the fastest FPGA-based LDPC decoder reported in the literature. A fabricated 0.13-mum CMOS bit-serial (660, 484) LDPC decoder is also presented. The decoder has a 300 MHz maximum clock frequency and a 3.3 Gbps throughput with a nominal 1.2-V supply and performs within 3 dB of the Shannon limit at a BER of 10-5. With more than 60% power saving gained by early termination, the decoder consumes 10.4 pJ/bit/iteration at Eb=N0=4dB. Coupling early termination with supply voltage scaling results in an even lower energy consumption of 2.7 pJ/bit/iteration with 648 Mbps decoding throughput. The proposed techniques demonstrate that the bit-serial fully-parallel architecture is preferred to memory-based partially-parallel architectures, both in terms of throughput and energy efficiency, for applications such as 10GBase-T which use medium-size LDPC code (e.g., 2048 bit) and require multi-Gbps decoding throughput.
Author: K. J. Ray Liu Publisher: Wiley-IEEE Press ISBN: Category : Mathematics Languages : en Pages : 704
Book Description
Electrical Engineering/Signal Processing High-Performance VLSI Signal Processing Innovative Architectures and Algorithms Volume 2 Systems Design And Applications The second volume in a two-volume set, High-Performance VLSI Signal Processing: Innovative Architectures and Algorithms brings together the most innovative papers in the field, focused introductory material, and extensive references. The editors present timely coverage of the latest design tools, design environments, and implementations of VLSI signal processing systems. These volumes will serve as vital resources for engineers who want a comprehensive knowledge of the extremely interdisciplinary field of high-performance VLSI processing. The editors provide a practical understanding of the merits of total system design through an insightful, synergistic presentation of methodology, architecture, and infrastructure. Each volume features: Major papers that span the wide range of research areas in the field Chapter introductions including historical perspectives Numerous applications-oriented design examples Coverage of current and future technological trends
Author: Kiran Kumar Gunnam Publisher: ISBN: Category : Languages : en Pages :
Book Description
The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. This dissertation presents the decoder architectures for regular and irregular LDPC codes that provide substantial gains over existing academic and commercial implementations. Several structured properties of LDPC codes and decoding algorithms are observed and are used to construct hardware implementation with reduced processing complexity. The proposed architectures utilize an on-the-fly computation paradigm which permits scheduling of the computations in a way that the memory requirements and re-computations are reduced. Using this paradigm, the run-time configurable and multi-rate VLSI architectures for the rate compatible array LDPC codes and irregular block LDPC codes are designed. Rate compatible array codes are considered for DSL applications. Irregular block LDPC codes are proposed for IEEE 802.16e, IEEE 802.11n, and IEEE 802.20. When compared with a recent implementation of an 802.11n LDPC decoder, the proposed decoder reduces the logic complexity by 6.45x and memory complexity by 2x for a given data throughput. When compared to the latest reported multi-rate decoders, this decoder design has an area efficiency of around 5.5x and energy efficiency of 2.6x for a given data throughput. The numbers are normalized for a 180nm CMOS process. Properly designed array codes have low error floors and meet the requirements of magnetic channel and other applications which need several Gbps of data throughput. A high throughput and fixed code architecture for array LDPC codes has been designed. No modification to the code is performed as this can result in high error floors. This parallel decoder architecture has no routing congestion and is scalable for longer block lengths. When compared to the latest fixed code parallel decoders in the literature, this design has an area efficiency of around 36x and an energy efficiency of 3x for a given data throughput. Again, the numbers are normalized for a 180nm CMOS process. In summary, the design and analysis details of the proposed architectures are described in this dissertation. The results from the extensive simulation and VHDL verification on FPGA and ASIC design platforms are also presented.
Author: Marghoob Mohiyuddin
Author: Marghoob Mohiyuddin
Author: Xinmiao Zhang
Author: Xiaohua Tian
Author: Jinjia Zhou
Author: Sabih H. Gerez
Author: Engling Yeo
Author: Ahmad Darabiha
Author: K. J. Ray Liu
Author: Yanni Chen
Author: Kiran Kumar Gunnam