Author: Jiayong LePublisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
Variation-aware Timing Analysis and Optimization for Digital ICs
Author: Jiayong LeTechniques for Variation Aware Modeling in Static Timing Analysis of Integrated Circuits
Author: Suryanarayana PendelaPublisher:
ISBN:
Category :
Languages : en
Pages : 95
Book Description
Much of the Semiconductor Industry's success can be attributed to Moore's law which states that the number of transistors on an integrated circuit would double approximately every two years. Semiconductor industry has ever since progressed from designs with a few hundred transistors to today's complex designs incorporating millions of transistors. The current era of nanometer technologies threatens to impact the sustainability of Moore's law with random variations in the manufacturing process impacting yield in a big way. Considerable research efforts have since been devoted to account for these variations leading to a new paradigm called Design for Manufacturing (DFM). Traditional Static Timing Analysis (STA) has given way to Statistical Static Timing Analysis (SSTA) techniques wherein the parameters considered are treated as random variables with assigned probability distribution functions. However, SSTA is still not seen as a mature flow for commercial adoption, owing to the inherent complex nature of the SSTA algorithms. In this thesis, we propose an alternate framework to STA under the presence of process variations using Interval Valued Static Timing Analysis (IVSTA). Process variations are accounted for by using a macro-modeling framework providing an efficient and fast timing analysis technique. Results on standard benchmarks show that IVSTA can predict the timing slack by a margin of 5-10% error and huge improvement of runtime compared to traditional corner based analysis. The framework involves a one-time characterization of the standard cell library and can be incorporated without much modification to the design flow. An iterative optimization framework using IVSTA engine is also presented which optimizes a routed netlist for variations at a minimum penalty of area and power.
Circuit Performance Verification and Optimization in the Presence of Variability
Author: Sari OnaissiPublisher:
ISBN: 9780494780787
Category :
Languages : en
Pages : 306
Book Description
The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of these variations on logic cell and interconnect delays has introduced challenges to both circuit performance (timing) verification and optimization. In order for us to fully take advantage of the benefits of technology scaling, it is essential that "variation-aware" techniques for performance verification and optimization be developed and used in modern design flows.In this thesis such techniques for both performance verification and optimization are presented. First, we present a fast method for finding the worst-case slacks over all process and environmental corners. This method uses the standard set of PVT corners available in industry, and provides large runtime gains while maintaining a high degree of accuracy. After that, we propose an efficient block-based parameterized timing analysis technique that can accurately capture circuit delays at every point in the parameter space, by reporting all paths that can become critical. This method employs parameterized static timing analysis (PSTA) variability models, and allows one to easily examine local robustness to parameters in different regions of the parameter space. Next, we introduce an optimization method that alters clock network lines so that a circuit meets its timing constraints at all PVT settings under PSTA variability models. This is formulated as a Linear Program (LP), which is based on a clock skew optimization formulation, and as a result it can be solved efficiently. Finally, we present a method that uses characterized, pre-silicon, PSTA variational timing models to identify speedpaths that can best explain the observed delay measurements during silicon debug. This is a crucial step, required for both "fixing"' failing paths and for accurate learning from silicon data.
Lifetime Reliability-aware Design of Integrated Circuits
Author: Mohsen RajiPublisher: Springer Nature
ISBN: 3031153456
Category : Technology & Engineering
Languages : en
Pages : 113
Book Description
This book covers the state-of-the-art research in design of modern electronic systems used in safety-critical applications such as medical devices, aircraft flight control, and automotive systems. The authors discuss lifetime reliability of digital systems, as well as an overview of the latest research in the field of reliability-aware design of integrated circuits. They address modeling approaches and techniques for evaluation and improvement of lifetime reliability for nano-scale CMOS digital circuits, as well as design algorithms that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. In addition to developing lifetime reliability analysis and techniques for clocked storage elements (such as flip-flops), the authors also describe analysis and improvement strategies targeting commercial digital circuits.
Timing Analysis and Optimization of Sequential Circuits
Author: Naresh MaheshwariPublisher: Springer Science & Business Media
ISBN: 1461556376
Category : Technology & Engineering
Languages : en
Pages : 202
Book Description
Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: Algorithms for sequential timing analysis Fast algorithms for clock skew optimization and their applications Efficient techniques for retiming large sequential circuits Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Author: José L. AyalaPublisher: Springer
ISBN: 3642361579
Category : Computers
Languages : en
Pages : 266
Book Description
This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.
Nanoelectronic Mixed-Signal System Design
Author: Saraju MohantyPublisher: McGraw Hill Professional
ISBN: 0071823034
Category : Technology & Engineering
Languages : en
Pages : 829
Book Description
Covering both the classical and emerging nanoelectronic technologies being used in mixed-signal design, this book addresses digital, analog, and memory components. Winner of the Association of American Publishers' 2016 PROSE Award in the Textbook/Physical Sciences & Mathematics category. Nanoelectronic Mixed-Signal System Design offers professionals and students a unified perspective on the science, engineering, and technology behind nanoelectronics system design. Written by the director of the NanoSystem Design Laboratory at the University of North Texas, this comprehensive guide provides a large-scale picture of the design and manufacturing aspects of nanoelectronic-based systems. It features dual coverage of mixed-signal circuit and system design, rather than just digital or analog-only. Key topics such as process variations, power dissipation, and security aspects of electronic system design are discussed. Top-down analysis of all stages--from design to manufacturing Coverage of current and developing nanoelectronic technologies--not just nano-CMOS Describes the basics of nanoelectronic technology and the structure of popular electronic systems Reveals the techniques required for design excellence and manufacturability
Aging Aware Timing Analysis of Digital Integrated Circuits for Varying Use Profiles
Author: Veit B. KleebergerCircuit Timing and Leakage Analysis in the Presence of Variability
Author: Khaled R. HeloueEfficient Design of Variation-Resilient Ultra-Low Energy Digital Processors
Author: Hans ReyserhovePublisher: Springer
ISBN: 3030124851
Category : Technology & Engineering
Languages : en
Pages : 209
Book Description
This book enables readers to achieve ultra-low energy digital system performance. The author’s main focus is the energy consumption of microcontroller architectures in digital (sub)-systems. The book covers a broad range of topics extensively: from circuits through design strategy to system architectures. The result is a set of techniques and a context to realize minimum energy digital systems. Several prototype silicon implementations are discussed, which put the proposed techniques to the test. The achieved results demonstrate an extraordinary combination of variation-resilience, high speed performance and ultra-low energy.