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Author: B. L. Johnson Publisher: ISBN: Category : Languages : en Pages : 149
Book Description
This report describes the logic design and hardware implementation of an encoder and decoder for a large number of Reed-Solomon symbol error-correction codes. The logic implements a transform encoding and decoding algorithm that was previously described in Volume One. The hardware required to implement the critical steps in the encoding and decoding algorithm is described in depth. An analysis of the decoder's operational characteristics and hardware complexity is presented. A proof-of-concept breadboard configured with small-scale Schottky TTL components is also described.
Author: B. L. Johnson Publisher: ISBN: Category : Languages : en Pages : 149
Book Description
This report describes the logic design and hardware implementation of an encoder and decoder for a large number of Reed-Solomon symbol error-correction codes. The logic implements a transform encoding and decoding algorithm that was previously described in Volume One. The hardware required to implement the critical steps in the encoding and decoding algorithm is described in depth. An analysis of the decoder's operational characteristics and hardware complexity is presented. A proof-of-concept breadboard configured with small-scale Schottky TTL components is also described.
Author: J.K. Skwirzynski Publisher: Springer Science & Business Media ISBN: 9400951132 Category : Science Languages : en Pages : 690
Book Description
This volume contains the full proceedings of the Fourth Advanced Study Institute organised by myself and my colleagues in . * the field of Communication Theory and Allied Subjects. In the first Institute we associated the subject of signal processing in communication with that in control engineering. Then we concentrated on noise and random phenomena by bringing in as well the subject of stochastic calculus. The third time our subject was multi-user communication and associated with it, the important problem of assessing algorithmic complexity. This time we are concerned with the vast increase of computational power that is now available in communication systems processors and controllers. This forces a mathematical, algorithmic and structural approach to the solution of computational requirements and design problems, in contrast to previous heuristic and intuitive methods. We are also concerned with the interactions and trade-offs between the structure, speed, and complexity of a process, and between software and hardware implementations. At the previous Advanced Study Institute in this series, on Multi-User Communications, there was a session on computational complexity, applied particularly to network routing problems. It was the aim of this Institute to expand this topic and to link it with information theory, random processes, pattern analysis, and implementation aspects of communication processors. The first part of these proceedings concentrates on pattern and structure in communications processing. In organising this session I was greatly helped and guided by Professor P. G. Farrell and Professor J. L. Massey.
Author: Publisher: ISBN: Category : Languages : en Pages : 65
Book Description
One of the continuing concerns of the Low Cost Electronics project is the application of new technology to the implementation of error-correcting codes for reliable data communication. Our interest stems from the need for low- cost hardware to implement error-correction codes that exhibit significant coding gain on interference-resistant communication channels. Previous studies of coding gain led us to concentrate work on the implementation of the Reed- Solomon class of generalized BCH codes. This class of codes, although well- suited to the correction of both isolated random errors and random error bursts because of its optimum distance properties, continues to be genuinely in need of efficient decoding algorithms implemented by low-cost hardware. This report discusses in detail a transform decoding algorithm and its hardware implications, for the Reed-Solomon codes, that offer major simplifications relative to the conventional BCH decoding algorithm. A fast algorithm for encoding and syndrome computation is described. Modification of the error location process to accommodate erasures is also described. Also discussed are hardware implementation issues with a summary of design features and parameters to be incorporated in a future set of programmable integrated circuits for decoding a large number of Reed-Solomon codes.
Author: Publisher: ISBN: Category : Research Languages : en Pages : 1362
Book Description
Sections 1-2. Keyword Index.--Section 3. Personal author index.--Section 4. Corporate author index.-- Section 5. Contract/grant number index, NTIS order/report number index 1-E.--Section 6. NTIS order/report number index F-Z.
Author: B. L. Johnson
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