Author: Stanford University. Computer Systems LaboratoryPublisher:
ISBN:
Category : Electric fault location
Languages : en
Pages : 52
Book Description
Test generation and fault diagnosis for multiple faults in combinational circuits
Author: Stanford University. Computer Systems LaboratoryPublisher:
ISBN:
Category : Electric fault location
Languages : en
Pages : 52
Book Description
A Study of Fault Diagnosis of Sequential Logic Networks
Author: B. D. CarrollPublisher:
ISBN:
Category :
Languages : en
Pages : 25
Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
Multiple Faults in Combinational Logic
Author: H. G. ShahPublisher:
ISBN:
Category :
Languages : en
Pages : 72
Book Description
The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author).
Comprehensive Fault Diagnosis of Combinational Circuits
Author: David B. LavoPublisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 278
Book Description
Automated Multiple Fault Test Generation for Combinational Networks
Author: Robert A. HendrixPublisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.
Testing for multiple intermittent failures in combinational circuits by maximizing the probability of fault detection
Author: Stanford University Stanford Electronics Laboratories. Digital Systems LaboratoryPublisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 36
Book Description
Multiple Fault Diagnosis in Combinational Networks
Author: Charles Wei-Yuan ChaPublisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Fault Diagnosis in Digital Circuits
Author: Mohamed Saled Soliman MahmoudPublisher:
ISBN: 9780355460582
Category :
Languages : en
Pages :
Book Description
The goals of fault diagnosis are to ascertain whether faults are present in (fault detection) and to identify them (fault location). Fault location is commonly performed with the aid of a fault dictionary. Fault dictionaries are constructed via fault simulation under the single fault assumption. The single fault-model often assumes a circuit is tested often enough such that no more than one physical defect is likely to occur between two consecutive test applications. This strategy is not valid when one physical defect manifests itself as multiple faults. It is observed that the presence of redundant faults also invalidates the frequent testing strategy, since a redundant fault may mask the existence of a detectable fault. In all these situations, a multiple fault model is required. However, in almost all practical cases a fault dictionary for multiple faults is infeasible to generate due to an exponential number of equivalence classes. In this dissertation, we first present a VHDL-based CAD tool that integrates design error injection, simulation, and diagnosis for digital circuits. The tool uses an FPGA-based board to inject error models in the design and compute the error free and erroneous signatures of internal lines. The signatures are later used for detection and diagnosis of errors for the circuit under test (CUT). Several experiments were conducted to demonstrate the capabilities of the tool. The obtained results demonstrate that the tool could detect and locate the source faulty node(s) within the CUT. Then, a new approach for a developed fault diagnosis method. Our approach is based on an enhanced deduction algorithm, which processes the actual response (effect) of CUT, to determine fault situations (causes). The main tool of our approach processes the response to deduce the internal signal values. A multiple stuck at fault model is implicitly employed and no-fault enumeration is required. The enhanced deduction algorithm is applicable to complicated combinational circuits. The internal values obtained are used to determine fault situations in CUT compatible with the applied test T and the response. Our analysis can identify fault locations and values (s-a-0 or s-a-1). Our main result is that any stuck fault can be diagnosed. Preliminary results demonstrate that our technique always achieves great accuracy for detecting and locating the faults, saving a large amount of time, especially for more complicated combinational circuits. The problems solved by our procedure are using deterministic test vectors. We next present a new approach for a developed fault diagnosis method. Our approach is based on an enhanced deduction algorithm and a backtracking strategy which can be regarded as a recursive process of value justification in which we first justify (explain) the values obtained at the primary outputs (POs). To justify a (0) value on the output of a- NAND gate (assuming it is normal), we need all the gate inputs to be (1). To justify a (1) value we need at least one input to have value (0). All the known values of internal normal lines must be justified by values of their predecessors. When both 0 and 1 values have been deduced for a gate output and it is critical, it is identified as normal and all its currently known values are analyzed. In some cases, we need to decide to select one of the possible ways to justify a (1) value on the output of a- NAND gate. If a decision leads to an inconsistency (self-contradictory state) with the forward propagated value, the algorithm will backtrack to the last decision point and try an alternative decision. After a decision is made, all the implications resulting from that decision are performed. If no inconsistency is detected, a new decision point is necessary. Otherwise, a solution has been obtained. A solution is a set of values which could have occurred in the CUT, that is, a possible set of actual values. The main tool of our approach processes the response to deduce the internal signal values in all possible solutions.
Test Generation for Detecting Multiple Stuck Faults in Synchronous Sequential Circuits Using Boolean Difference and Transition Matrix Techniques
Author: Thiep V. NguyenPublisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
The Boolean difference is a mathematical concept which has proved its usefulness in the study of single and multiple stuck-at faults in combinational circuits. This tool of analysis was extended to cover multiple stuck-at faults in synchronous sequential circuits as well. In this dissertation, modifications to previous work are presented, together with the development of a new method for deriving the required shortest test sequence to detect a specified multiple fault. First, the vector Boolean difference technique is utilized to determine the input vector that will produce a difference in output between the fault-free and faulty circuits with both starting in the same initial state. If that detection cannot be achieved immediately, then the state transition matrices of both circuits are combined and used to form a matrix of detecting state pairs. Each of these pairs comprises of the present states of both circuits for which an output difference will be detected by an input vector. The detecting tree is then built leading the two circuits from the same initial state to the first detecting state found to complete the search for the shortest test sequence. Besides being able to identify, at an early stage, faults that are undetectable, this algorithm guarantees the generation of a shortest test sequence, if one exists, for every multiple stuck-at fault in a synchronous sequential circuit having a synchronizing sequence or a known initial state. A computer program was also written as a tool to automatically generate test sequences for detecting single or multiple faults in both combinational and synchronous sequential circuits.
Diagnosis and Reliable Design of Digital Systems
Author: Melvin A. BreuerPublisher: Computer Science Press, Incorporated
ISBN:
Category : Computers
Languages : en
Pages : 328
Book Description
Considers the problems of test generation, simulation, & reliability-enhancing design techniques for digital circuits & systems.