Sub-micron InP/GaAsSb/InP Double Heterojunction Bipolar Transistors for Ultra High-speed Digital Integrated Circuits PDF Download

Author: Urs Hammer
Publisher:
ISBN: 9783866283015
Category : Bipolar transistors
Languages : en
Pages : 265

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Author: Wei Quan
Publisher:
ISBN:
Category :
Languages : en
Pages :

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Author: M F Chang
Publisher: World Scientific
ISBN: 9814501069
Category : Technology & Engineering
Languages : en
Pages : 437

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Recent advances in communication, digital signal processing and computational systems demand very high performance electronic circuits. Heterojunction Bipolar Transistors (HBTs) have the potential of providing a more efficient solution to many key system requirements through intrinsic device advantages. This book reviews the present status of GaAs, InP and silicon-based HBT technologies and their applications to digital, analog, microwave and mixed-signal circuits and systems. It represents the first major effort to cover the complete scope of the HBT technology development in the past decade, starting from the fundamental device physics, material growth, device reliability, scaling, processing, modeling to advanced HBT integrated circuit design for various system applications.

Author: Martin W. Dvorak
Publisher:
ISBN:
Category : Bipolar transistors
Languages : en
Pages : 356

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Author: Tomas Krämer
Publisher:
ISBN: 9783869553931
Category :
Languages : en
Pages : 131

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Author: Benjamin Chu-Kung
Publisher:
ISBN:
Category :
Languages : en
Pages : 56

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Author: Nick Gengming Tao
Publisher:
ISBN:
Category : Bipolar transisitors
Languages : en
Pages : 318

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In recent years, GaAsSb/InP double heterojunction bipolar transistors (DHBTs) have been demonstrated to be promising alternatives to InP/InGaAs HBTs, for next generation microwave/millimeter wave applications and optoelectronic integrated circuits (OEICs). However, GaAsSb-based DHBTs featuring the novel base material and type-II band alignment have not been well studied. This thesis investigated type-II GaAsSb DHBTs in the following aspects: periphery surface recombination current, Kirk effect, two dimensional (2D) simulation and device optimization. The present work provided insights into device operation, and guidances for further device development. A series of physical models and parameters was implemented in 2D device simulations using ISE TCAD. Band gap narrowing (BGN) in the bases was characterized by comparing experimental and simulated results. Excellent agreements between the measured and simulated DC and RF results were achieved. Emitter size effects associated with the surface recombination current were experimentally characterized for emitter sizes of 0.5 by 6 to 80 by 80 square micrometer. The 2D simulations by implementing surface state models revealed the mechanism for the surface recombination current. Two device structures were proposed to diminish surface recombination current. Numerical simulations for type-II GaAsSb-InP base-collector (BC) junctions showed that conventional base "push-out" does not occur at high injection levels, and instead the electric field at the BC junction is reversed and an electron barrier at the base side evolves. The electron barrier was found to play an important role in the Kirk effect, and the electron tunnelling through the barrier delays the onset of the Kirk effect. This novel mechanism was supported by the measurement for GaAsSb/InP DHBTs with two base doping levels. The study also showed that the magnitude of the electric field at the BC junction at zero collector current directly affects onset of the Kirk effect. Finally, optimizations for the emitter, base and collector were carried out through 2D simulations. A thin InAlAs emitter, an (Al)GaAsSb compositionally graded base with band gap variance of 0.1eV, and a high n-type delta doping in the collector were proposed to simultaneously achieve high frequency performance, high Kirk current density and high breakdown voltage.

Author: Maria Alexandrova
Publisher:
ISBN:
Category :
Languages : en
Pages :

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Author: Andreas Dominic Kurth
Publisher: BoD – Books on Demand
ISBN: 3866287747
Category : Science
Languages : en
Pages : 282

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Heterogeneous systems on chip (HeSoCs) combine general-purpose, feature-rich multi-core host processors with domain-specific programmable many-core accelerators (PMCAs) to unite versatility with energy efficiency and peak performance. By virtue of their heterogeneity, HeSoCs hold the promise of increasing performance and energy efficiency compared to homogeneous multiprocessors, because applications can be executed on hardware that is designed for them. However, this heterogeneity also increases system complexity substantially. This thesis presents the first research platform for HeSoCs where all components, from accelerator cores to application programming interface, are available under permissive open-source licenses. We begin by identifying the hardware and software components that are required in HeSoCs and by designing a representative hardware and software architecture. We then design, implement, and evaluate four critical HeSoC components that have not been discussed in research at the level required for an open-source implementation: First, we present a modular, topology-agnostic, high-performance on-chip communication platform, which adheres to a state-of-the-art industry-standard protocol. We show that the platform can be used to build high-bandwidth (e.g., 2.5 GHz and 1024 bit data width) end-to-end communication fabrics with high degrees of concurrency (e.g., up to 256 independent concurrent transactions). Second, we present a modular and efficient solution for implementing atomic memory operations in highly-scalable many-core processors, which demonstrates near-optimal linear throughput scaling for various synthetic and real-world workloads and requires only 0.5 kGE per core. Third, we present a hardware-software solution for shared virtual memory that avoids the majority of translation lookaside buffer misses with prefetching, supports parallel burst transfers without additional buffers, and can be scaled with the workload and number of parallel processors. Our work improves accelerator performance for memory-intensive kernels by up to 4×. Fourth, we present a software toolchain for mixed-data-model heterogeneous compilation and OpenMP offloading. Our work enables transparent memory sharing between a 64-bit host processor and a 32-bit accelerator at overheads below 0.7 % compared to 32-bit-only execution. Finally, we combine our contributions to a research platform for state-of-the-art HeSoCs and demonstrate its performance and flexibility.

Author: Matheus Cavalcante
Publisher: BoD – Books on Demand
ISBN: 3866288018
Category :
Languages : en
Pages : 224

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Book Description
In his seminal Turing Award Lecture, Backus discussed the issues stemming from the word-at-a-time style of programming inherited from the von Neumann computer. More than forty years later, computer architects must be creative to amortize the von Neumann Bottleneck (VNB) associated with fetching and decoding instructions which only keep the datapath busy for a very short period of time. In particular, vector processors promise to be one of the most efficient architectures to tackle the VNB, by amortizing the energy overhead of instruction fetching and decoding over several chunks of data. This work explores vector processing as an option to build small and efficient processing elements for large-scale clusters of cores sharing access to tightly-coupled L1 memory