Author: Koyelia KhatunPublisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
Power electronic is the prominent enabling technologies for the uninterruptible power supply (UPS), renewable energy sources, fuel cells, energy storage, electric transportation, electrical appliances and industrial processes. Owing to the challenges to safety, high step-up ratio, galvanic isolation, high-frequency (HF) transformer isolated topologies are introduced. Currentfed topologies offer the merits of high voltage gain, stiff input current and reduced peak currents. The major limitations of current-fed converters is the requirement of snubber circuit to clamp the turn-off voltage spike across the semiconductor devices. Passive snubbers leads to low efficiency as the energy absorbed by the clamping capacitor is dissipated in the resistor. Active-clamping results in better efficiency and simultaneously achieves zero voltage switching (ZVS) of the semiconductor devices. However, it needs floating active device(s) and high value of HF clamp capacitor for the effective voltage clamping. In addition, it suffers from the demerits of high current peak, high circulating current at light load, and reduced voltage gain. A new modulation technique was proposed to modulate secondary side controlled devices to clamp this voltage spike across the primary side devices eliminating the requirement of external snubber circuit. Steady-state analysis, power circuit design and steady-state performance have been reported for such class of snubberless naturally clamped current-fed converters. However, small signal analysis, control design, implementation, and transient/dynamic performance have not been studied yet. The objectives of this thesis are to present small signal analysis, closed loop control design, and demonstrate the transient performance through simulation and experimentation of the snubberless naturally clamped current-fed half-bridge and push-pull dc-dc converter topologies. Small signal model has been derived using state space averaging. Closed loop control design is done employing two-loop average current control. Simulation results using PSIM 11.1.64 are reported to verify the converter performance with the designed controller. Experimental results from a 250W proof-of-concept hardware prototype are demonstrated to show the transient performance of current-fed half-bridge and push-pull dc-dc converter topologies