Shared Virtual Memory for Heterogeneous Embedded Systems on Chips PDF Download

Author: Pirmin Robert Vogel
Publisher:
ISBN: 9783866286238
Category :
Languages : en
Pages : 197

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Author: Pirmin Vogel
Publisher:
ISBN:
Category :
Languages : en
Pages :

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Author: Andreas Dominic Kurth
Publisher: BoD – Books on Demand
ISBN: 3866287747
Category : Science
Languages : en
Pages : 282

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Heterogeneous systems on chip (HeSoCs) combine general-purpose, feature-rich multi-core host processors with domain-specific programmable many-core accelerators (PMCAs) to unite versatility with energy efficiency and peak performance. By virtue of their heterogeneity, HeSoCs hold the promise of increasing performance and energy efficiency compared to homogeneous multiprocessors, because applications can be executed on hardware that is designed for them. However, this heterogeneity also increases system complexity substantially. This thesis presents the first research platform for HeSoCs where all components, from accelerator cores to application programming interface, are available under permissive open-source licenses. We begin by identifying the hardware and software components that are required in HeSoCs and by designing a representative hardware and software architecture. We then design, implement, and evaluate four critical HeSoC components that have not been discussed in research at the level required for an open-source implementation: First, we present a modular, topology-agnostic, high-performance on-chip communication platform, which adheres to a state-of-the-art industry-standard protocol. We show that the platform can be used to build high-bandwidth (e.g., 2.5 GHz and 1024 bit data width) end-to-end communication fabrics with high degrees of concurrency (e.g., up to 256 independent concurrent transactions). Second, we present a modular and efficient solution for implementing atomic memory operations in highly-scalable many-core processors, which demonstrates near-optimal linear throughput scaling for various synthetic and real-world workloads and requires only 0.5 kGE per core. Third, we present a hardware-software solution for shared virtual memory that avoids the majority of translation lookaside buffer misses with prefetching, supports parallel burst transfers without additional buffers, and can be scaled with the workload and number of parallel processors. Our work improves accelerator performance for memory-intensive kernels by up to 4×. Fourth, we present a software toolchain for mixed-data-model heterogeneous compilation and OpenMP offloading. Our work enables transparent memory sharing between a 64-bit host processor and a 32-bit accelerator at overheads below 0.7 % compared to 32-bit-only execution. Finally, we combine our contributions to a research platform for state-of-the-art HeSoCs and demonstrate its performance and flexibility.

Author: Gitu Jain
Publisher: Elsevier Inc. Chapters
ISBN: 0128073381
Category : Technology & Engineering
Languages : en
Pages : 54

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Unlike general-purpose computing systems, multicore embedded systems are designed with a specific application in mind. The memory access patterns for the application can be used to customize the memory architecture of the device. This chapter presents a synopsis of memory types and architecture commonly used in multicore embedded systems. It examines the many trade-offs that can be considered when designing the memory architecture. It considers factors such as whether the memory should be shared or distributed among the multiple cores; will the cores benefit from memory cache and what should the cache configuration be; is there a cache coherency protocol used; should there be other memory types on the device such as scratch pad SRAMs and eDRAMs; does the device use a DMA for memory transfers, and other factors. It provides guidance to the embedded system designers to tailor the memory architecture to their needs.

Author: Abhishek Bhattacharjee
Publisher: Springer Nature
ISBN: 3031017579
Category : Technology & Engineering
Languages : en
Pages : 168

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This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space. Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries. However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.

Author: David R. Kaeli
Publisher: Morgan Kaufmann
ISBN: 0128016493
Category : Computers
Languages : en
Pages : 330

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Heterogeneous Computing with OpenCL 2.0 teaches OpenCL and parallel programming for complex systems that may include a variety of device architectures: multi-core CPUs, GPUs, and fully-integrated Accelerated Processing Units (APUs). This fully-revised edition includes the latest enhancements in OpenCL 2.0 including: • Shared virtual memory to increase programming flexibility and reduce data transfers that consume resources • Dynamic parallelism which reduces processor load and avoids bottlenecks • Improved imaging support and integration with OpenGL Designed to work on multiple platforms, OpenCL will help you more effectively program for a heterogeneous future. Written by leaders in the parallel computing and OpenCL communities, this book explores memory spaces, optimization techniques, extensions, debugging and profiling. Multiple case studies and examples illustrate high-performance algorithms, distributing work across heterogeneous systems, embedded domain-specific languages, and will give you hands-on OpenCL experience to address a range of fundamental parallel algorithms. Updated content to cover the latest developments in OpenCL 2.0, including improvements in memory handling, parallelism, and imaging support Explanations of principles and strategies to learn parallel programming with OpenCL, from understanding the abstraction models to thoroughly testing and debugging complete applications Example code covering image analytics, web plugins, particle simulations, video editing, performance optimization, and more

Author: Chit-Ho Dominic Hung
Publisher: Open Dissertation Press
ISBN: 9781361009222
Category : Computers
Languages : en
Pages : 174

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This dissertation, "A Software Shared Virtual Memory System With Three Way Coherence Protocols on the Intel Single-chip Cloud Computer" by Chit-ho, Dominic, Hung, 熊哲皓, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. Abstract: With the advancement of design and fabrication of high-performance integrated circuits technology, it is foreseeable that processors with more than 1,000 cores per die will appear in the near future. However, these many-core architectures have introduced a lot of challenges at the memory system level, such as complicated cache coherence and limited memory access speed, to name a few. This thesis focuses on one prominent many-core prototype - the Intel's Single-chip Cloud Computer (SCC). The SCC architecture does not provide hardware cache coherency. Instead, it relies on on-chip programmable memory. The baseline coherence protocol for the SCC is the Software Managed Coherence (SMC) layer. To achieve memory consistency, it accesses shared memory without part of the typical cache hierarchy for efficient invalidation and flushing. We found that performance provided by this coherence layer in this manner is sub-optimal because accesses of shared memory would all turn into data update messages within the network mesh. As cache locality could not be exploited to its full potential, the execution pipelines stall much often for memory fetches from outside the chip. This research is to address the performance problem of shared virtual memory consistency for this cache in-coherent architecture. Oriented at sitting data on-chip as much as possible to reduce memory accesses external to the chip, we propose two techniques to leverage the cache hierarchy to full and reside data in the on-chip scratchpad memory. First, targeted at the architectural specificity of the hardware, we redesigned traditional software distributed shared memory (SDSM) to allow shared data be treated transparently like private memory so the cache hierarchy can be fully utilised without sacrificing memory consistency. Second, we propose a distance-aware page allocation scheme that samples access frequencies and select the most frequently-recently used pages to be stored on the on-chip scratchpad memory. Our experimental results show that our first technique, the ordinary SDSM outperforms the current SMC approach by 5 times. Moreover, in some cases, with the second technique that is based on scratchpad memory, our proposed system outperforms further by an additional 1.57 times. Our experiments also demonstrated that the SMC approach is not scalable due to congestion of the network mesh by coherence traffic generated while the two new approaches continued to scale well. The main contribution of this research is the implementation of a cache coherence software library system built for an architecture that comes with non-coherent cache hardware and just relies on software-defined cache. This new cache hierarchy has evidently opened the door for smarter and faster inter-processor-core data sharing without the need of complicated cache coherence hardware. Subjects: Distributed shared memory Cloud computing

Author: Li, K. (Kai)
Publisher: Computer Systems Research Institute
ISBN:
Category : Sun computers
Languages : en
Pages : 22

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Author: Matheus Cavalcante
Publisher: BoD – Books on Demand
ISBN: 3866288018
Category :
Languages : en
Pages : 224

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In his seminal Turing Award Lecture, Backus discussed the issues stemming from the word-at-a-time style of programming inherited from the von Neumann computer. More than forty years later, computer architects must be creative to amortize the von Neumann Bottleneck (VNB) associated with fetching and decoding instructions which only keep the datapath busy for a very short period of time. In particular, vector processors promise to be one of the most efficient architectures to tackle the VNB, by amortizing the energy overhead of instruction fetching and decoding over several chunks of data. This work explores vector processing as an option to build small and efficient processing elements for large-scale clusters of cores sharing access to tightly-coupled L1 memory

Author: Miguel Peón Quirós
Publisher: Springer Nature
ISBN: 3030374327
Category : Technology & Engineering
Languages : en
Pages : 214

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This book defines and explores the problem of placing the instances of dynamic data types on the components of the heterogeneous memory organization of an embedded system, with the final goal of reducing energy consumption and improving performance. It is one of the first to cover the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures, presenting a complete methodology that can be easily adapted to real cases and work flows. The authors discuss how to improve system performance and energy consumption simultaneously. Discusses the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures; Presents a complete methodology that can be adapted easily to real cases and work flows; Offers hints on how to improve system performance and energy consumption simultaneously.