Process Integration and Performance Evaluation of Ge-based Quantum Well Channel MOSFETs for Sub-22nm Node Digital CMOS Logic Technology PDF Download

Author: Se-Hoon Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 320

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Book Description
Since metal-oxide-semiconductor (MOS) device was first reported around 1959 and utilized for integrated circuits in 1961, complementary MOS technology has become the mainstream of semiconductor industry. Its performance has been improved based on scaling of dimensions of MOS field-effect-transistors (MOSFET) in accordance with Moore's law, which states that the density of MOSFETs due to scaling approximately doubles every two years. Entering into sub-100nm regime caused a lot of challenges. Traditional way of scaling no longer provided performance enhancement of individual MOSFETs. Increased channel doping which is required to prevent degradation of device electrostatics from short channel effects caused carrier mobility degradation. New inventions needed to be incorporated to sustain performance enhancement trend with scaling. Implementation of process induced strained Si technology allowed mobility enhancement, and high-K/metal gate instead of conventional poly-Si/SiO2 allowed continuing electrical gate oxide thickness scaling, hence extending the life span of Moore's law. As we are now moving toward 22nm logic technology and below, new concerns have been rapidly aroused. Controlling power consumption and performance variability are becoming as important as developing scaled devices with enhanced performance. Expandability of strained-Si channel technology via process induced strain also faces increasing complexity from ever tighter gate pitch and difficulties in controlling defect level with the channel stress enhancement techniques. At the same time, long-lasting planar MOSFET architecture also faces serious challenges due to the limits of controlling short channel effects. New paradigms and pathways for future technology seems to be required. As a result, new material sets, new device architectures and concepts are being vigorously explored in the literature. These new trends can be categorized into three groups: MOSFET structure with (non-Si) high mobility channel materials, advanced (non-planar) MOSFET structures, and MOSFET-type structures with new device operation concepts such as tunneling FETs. This dissertation presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology.

Author: Jacopo Franco
Publisher: Springer Science & Business Media
ISBN: 9400776632
Category : Technology & Engineering
Languages : en
Pages : 203

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Book Description
Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process - and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes.

Author: Winston Chern
Publisher:
ISBN:
Category :
Languages : en
Pages : 167

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Book Description
Moore's law has driven technological improvements for decades by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As ever-smaller footprints are desired, power density limitations and performance degradation require more innovations on all fronts. Recently introduced improvements to integrated circuits are high-K and metal gate for MOSFETs (45-nm node onward), the FinFET (22-nm node onward) and air gaps between copper interconnects (14-nm node) illustrating that at every new technology node there needs to be a materials or process-related improvement to reduce power and maintain performance. Other approaches are also being explored or taken to further improve the MOSFET performance in future technology nodes, namely use of channel materials with higher carrier mobility such as SiGe and Ge for p-MOSFETs, III-V compound semiconductors for n-MOSFETs and steep subthreshold swing devices such as tunnel field effect transistors (TFETs). This work evaluates both approaches utilizing germanium (Ge) and strained-Ge as a material to understand the benefits and drawbacks to both approaches. Hypothetically, high carrier mobility and velocity channel materials can lower the overall power consumption because lower power supply voltage is required to obtain the same amount of current. Germanium and strained-Ge are candidates for the channel material of p-MOSFETs. MOSFETs made using Ge and strained-Ge as the channel material are evaluated based upon the ITRS roadmap requirements using experimental results in this work and data from literature. The approach for using TFETs was evaluated in this work also using germanium as a channel material. TFETs can have a steep subthreshold swing (SS), better than the minimum of 60 mV/decade at room temperature for a MOSFET, which also reduces the total power and supply voltage required for operation. The reduced SS is hypothetically achieved through the band-to-band tunneling which allows for the filtering of the Fermi-tail distribution of carriers. Experimentally, TFETs have not generally shown the steeper than Fermi-tail SS promised by the theory and this work uses both results from fabricated strained-Si/strained-Ge TFETs as well as modeling to explain why this has been the case. The challenges for both technologies are outlined in this thesis and suggestions are made on approaches to tackling their respective intrinsic problems from the point of view of Ge-based devices.

Author: Salvador Pinillos Gimenez
Publisher: Morgan & Claypool Publishers
ISBN: 1627054820
Category : Technology & Engineering
Languages : en
Pages : 83

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Book Description
This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.

Author: Se-hoon Lee
Publisher: LAP Lambert Academic Publishing
ISBN: 9783846506868
Category :
Languages : en
Pages : 160

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Book Description
This work presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology.

Author: Bruce W. Smith
Publisher: CRC Press
ISBN: 1351643444
Category : Technology & Engineering
Languages : en
Pages : 770

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Book Description
The completely revised Third Edition to the bestselling Microlithography: Science and Technology provides a balanced treatment of theoretical and operational considerations, from fundamental principles to advanced topics of nanoscale lithography. The book is divided into chapters covering all important aspects related to the imaging, materials, and processes that have been necessary to drive semiconductor lithography toward nanometer-scale generations. Renowned experts from the world’s leading academic and industrial organizations have provided in-depth coverage of the technologies involved in optical, deep-ultraviolet (DUV), immersion, multiple patterning, extreme ultraviolet (EUV), maskless, nanoimprint, and directed self-assembly lithography, together with comprehensive descriptions of the advanced materials and processes involved. New in the Third Edition In addition to the full revision of existing chapters, this new Third Edition features coverage of the technologies that have emerged over the past several years, including multiple patterning lithography, design for manufacturing, design process technology co-optimization, maskless lithography, and directed self-assembly. New advances in lithography modeling are covered as well as fully updated information detailing the new technologies, systems, materials, and processes for optical UV, DUV, immersion, and EUV lithography. The Third Edition of Microlithography: Science and Technology authoritatively covers the science and engineering involved in the latest generations of microlithography and looks ahead to the future systems and technologies that will bring the next generations to fruition. Loaded with illustrations, equations, tables, and time-saving references to the most current technology, this book is the most comprehensive and reliable source for anyone, from student to seasoned professional, looking to better understand the complex world of microlithography science and technology.

Author: Ashish Agrawal
Publisher:
ISBN:
Category :
Languages : en
Pages :

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Book Description
Continual scaling of silicon (Si) complementary metal-oxide-semiconductor (CMOS) into deep sub-20nm regime meets some immense challenges which hinder the CMOS development. High performance III-V n-channel quantum well (QW) field effect transistors have been demonstrated with InGaAs channel. However, for complementary logic implementation, there is a significant challenge for identifying high mobility p-channel pMOS candidates. Among the most attractive candidates for pMOS are compressively strained InSb, InGaSb and Ge QW heterostructures which feature high hole mobility. The motivation of this work stems from establishing a comprehensive understanding of the transport in these QW heterostructures, extracting dominant transport limiting mechanisms and subsequently suggesting key design parameters that would enable the selection of the best channel material.Low field transport is experimentally analyzed and compared for compressively strained InSb and Ge QW heterostructures. Comprehensive bandstructure calculation and scattering analysis was performed incorporating the effect of strain and quantization to model the experimental mobility. Strained germanium which has very high hole mobility has been analyzed to be the promising alternative channel material for the future CMOS applications.Compressively strained Ge QW FinFETs with Si0.3Ge0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm Wfin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-k dielectric HfO2/Al2O3/GeOx gate stack achieving ultrathin EOT of 0.7nm with low DIT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si0.3Ge0.7 buffer on bulk Si substrate exhibiting peak uH=700 cm2/Vs, uH=220 cm2/Vs at 10^13 /cm2 hole density. The s-Ge FinFETs achieve the highest u*Cmax of 3.1x10^-4 F/Vs resulting in 5X higher ION over unstrained Ge FinFETs. Short channel performance is analyzed, discussed and benchmarked with literature.

Author: William Hsu (Ph. D.)
Publisher:
ISBN:
Category :
Languages : en
Pages : 268

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Book Description
Power dissipation has become one of the most significant impediments to continued scaling of complementary metal-oxide-semiconductor (CMOS) technology. Two approaches have been proposed for enabling supply power scaling: (i) reduction of subthreshold swing (SS) with novel operation mechanisms, and (ii) increasing of ON-current with high mobility materials or advanced device architectures. In this work, two alternative devices, tunnel field-effect transistors (TFETs) and Ge-channel MOSFETs, are being explored as possible solutions to these two approaches, respectively. TFETs have the potential to achieve a SS steeper than the thermionic emission defined limit of 60 mV/dec at room temperature to which MOSFETs are subject and, thus, enable lower voltage, lower power logic. On the other hand, Ge is promising as the enabler for high mobility channel, offering the potential to further enhance ON-current. The compatibility with conventional Si CMOS manufacturing makes Ge very attractive compared to other high mobility materials (e.g. III-V). In the first part, a Si-technology compatible Si/Ge heterojunction TFET is proposed. The device design utilizes a strained-Si/strained-Ge vertical heterojunction to provide a staggered-gap band alignment with small effective band gap and gate normal tunneling. Performance evaluation by simulation suggests that the device has the potential to be competitive with modern MOSFETs. In addition, device design guidelines in terms of electrostatic control are discussed while considering the quantum effects. In the second part, we focus on source/drain junction engineering for Ge CMOS. For n-type junctions, advanced activation scheme using non-melt sub-millisecond laser spike annealing is utilized to demonstrate excellent diffusion control and high activation level. For p-type junctions, novel BF implantation is shown to offer a higher B activation level and a shallower junction depth in Ge as compared to B and BF2 implantations. The detail diffusion mechanism of B in the presence of F is studied. High performance Ge n-type and p-type diodes are obtained along with significant reduction of contact resistance, and integration in a MOSFET process flow.

Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 161

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Book Description
InGaAs is a promising candidate as an n-type channel material for future CMOS due to its superior electron transport properties. Great progress has taken place recently in demonstrating InGaAs MOSFETs for this goal. Among possible InGaAs MOSFET architectures, the recessed-gate design is an attractive option due to its scalability and simplicity. In this thesis, a novel self-aligned recessed-gate fabrication process for scaled InGaAs Quantum-Well MOSFETs (QW-MOSFETs) is developed. The device architectural design emphasizes scalability, performance and manufacturability by making extensive use of dry etching and Si-compatible materials. The fabrication sequence yields precise control of all critical transistor dimensions. This work achieved InGaAs MOSFETs with the shortest gate length (Lg=20 nm), and MOSFET arrays with the smallest contact size (Lc=40 nm) and smallest pitch size (Lp=150 nm), at the time when they were made. Using a wafer bonding technique, InGaAs MOSFETs were also integrated onto a silicon substrate. The fabricated transistors show the potential of InGaAs to yield devices with well-balanced electron transport, electrostatic integrity and parasitic resistance. A device design optimized for transport exhibits a transconductance of 3.1 mS/[mu]m, a value that matches the best III-V high-electron-mobility transistors (HEMTs). The precise fabrication technology developed in this work enables a detailed study of the impact of channel thickness scaling on device performance. The scaled III-V device architecture achieved in this work has also enabled new device physics studies relevant for the application of InGaAs transistors for future logic. A particularly important one is OFF-state leakage. For the first time, this work has unambiguously identified band-to-band tunneling (BTBT) amplified by a parasitic bipolar effect as the cause of excess OFF-state leakage current in these transistors. This finding has important implications for future device design

Author: Peng Zheng
Publisher:
ISBN:
Category :
Languages : en
Pages : 72

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Book Description
The remarkable proliferation of information and communication technology (ICT) - which has had dramatic economic and social impact in our society - has been enabled by the steady advancement of integrated circuit (IC) technology following Moore's Law, which states that the number of components (transistors) on an IC "chip" doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density -> lower cost / better performance -> semiconductor market growth -> technology advancement -> higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology. Gate-all-around (GAA) FETs are anticipated to be adopted in future generations, to enable ultimate gate-length scaling. This work firstly benchmarks the performance of GAA MOSFETs against that of the FinFETs at 10 nm gate length (anticipated for 4/3 nm CMOS technology). Variability in transistor performance due to systematic and random variations is estimated with the aid of technology computer-aided design (TCAD) three-dimensional (3-D) device simulations, for both device structures. The yield of six-transistor (6-T) SRAM cells implemented with these advanced MOSFET structures is then investigated via a calibrated physically based compact model. The benefits of GAA MOSFET technology for lowering the minimum operating voltage (Vmin) and area of 6-T SRAM cells to facilitate increased transistor density following Moore's Law are assessed. In order to achieve similar (or even better) layout area efficiency as a FinFET, a GAA FET must comprise stacked nanowires (NWs), which would add significant fabrication process complexity. This is because stacked NWs are formed by epitaxial growth of relatively thick (>10 nm) Si1-xGex sacrificial layers between Si channel layers to accommodate gate-dielectric/gate-metal/gate-dielectric layers in-between the NWs, so that fin structures with very high aspect ratio (>10:1 height:width) must be etched prior to selective removal of the Si1-xGex layers. Also, it will be more difficult to implement multiple gate-oxide thicknesses with GAA FET technology for system-on-chip (SoC) applications. In this work, a novel stacked MOSFET design, the inserted-oxide FinFET (iFinFET), is proposed to mitigate these issues. With enhanced performance due to improved electrostatic integrity and minimal added process complexity, iFinFET provides a pathway for future CMOS technology scaling. Advancements in lithography have been key to sustaining Moore's Law. Due to the low transmittance of blank mask materials and/or the availability of high-intensity light sources for wavelengths shorter than 193 nm, the semiconductor industry has resorted to "multiple-patterning" techniques to increase the density of linear features patterned on a chip. The additional cost due to extra lithography or deposition and etch processes associated with multiple-patterning techniques threaten to bring Moore's Law to an end, stunting the growth of the entire ICT industry. This work proposes an innovative cost-efficient patterning method via tilted ion implantation (TII) for achieving sub-lithographic features and/or doubling the density of features, one that is capable of achieving arbitrarily small feature size, self-aligned to pre-existing features on the surface. The proposed technique can be used to pattern IC layers in both front-end-of-line (FEOL) and low-temperature back-end-of-line (BEOL) processes. With feature size below 10 nm experimentally demonstrated, TII-enhanced patterning offers a cost-effective pathway to extend the era of Moore's Law. The primary reason for increasing the number of components per IC, enabled by advancement of IC manufacturing technology, was (and still) is lower cost. Although different opinions are held throughout industry regarding the "cost-per-transistor" trend, reduction in IC manufacturing cost is the key challenge as technology advances to extend Moore's Law. This work summarizes a survey regarding IC manufacturing cost throughout the semiconductor industry. Two case studies reveal that the iFinFET technology and TII double patterning technique have significant economic merit in future technology nodes, especially beyond the 7 nm technology node where the industry does not yet have clear solutions. The proposed technologies can enable the semiconductor industry to extend the era of Moore's Law, with broad economic and social benefit to society.