Author: Israel Koren
Publisher: Morgan Kaufmann
ISBN: 0128181060
Category : Computers
Languages : en
Pages : 418
Book Description
Fault-Tolerant Systems, Second Edition, is the first book on fault tolerance design utilizing a systems approach to both hardware and software. No other text takes this approach or offers the comprehensive and up-to-date treatment that Koren and Krishna provide. The book comprehensively covers the design of fault-tolerant hardware and software, use of fault-tolerance techniques to improve manufacturing yields, and design and analysis of networks. Incorporating case studies that highlight more than ten different computer systems with fault-tolerance techniques implemented in their design, the book includes critical material on methods to protect against threats to encryption subsystems used for security purposes. The text's updated content will help students and practitioners in electrical and computer engineering and computer science learn how to design reliable computing systems, and how to analyze fault-tolerant computing systems. - Delivers the first book on fault tolerance design with a systems approach - Offers comprehensive coverage of both hardware and software fault tolerance, as well as information and time redundancy - Features fully updated content plus new chapters on failure mechanisms and fault-tolerance in cyber-physical systems - Provides a complete ancillary package, including an on-line solutions manual for instructors and PowerPoint slides
Fault-Tolerant Systems
Author: Israel Koren
Publisher: Morgan Kaufmann
ISBN: 0128181060
Category : Computers
Languages : en
Pages : 418
Book Description
Fault-Tolerant Systems, Second Edition, is the first book on fault tolerance design utilizing a systems approach to both hardware and software. No other text takes this approach or offers the comprehensive and up-to-date treatment that Koren and Krishna provide. The book comprehensively covers the design of fault-tolerant hardware and software, use of fault-tolerance techniques to improve manufacturing yields, and design and analysis of networks. Incorporating case studies that highlight more than ten different computer systems with fault-tolerance techniques implemented in their design, the book includes critical material on methods to protect against threats to encryption subsystems used for security purposes. The text's updated content will help students and practitioners in electrical and computer engineering and computer science learn how to design reliable computing systems, and how to analyze fault-tolerant computing systems. - Delivers the first book on fault tolerance design with a systems approach - Offers comprehensive coverage of both hardware and software fault tolerance, as well as information and time redundancy - Features fully updated content plus new chapters on failure mechanisms and fault-tolerance in cyber-physical systems - Provides a complete ancillary package, including an on-line solutions manual for instructors and PowerPoint slides
Publisher: Morgan Kaufmann
ISBN: 0128181060
Category : Computers
Languages : en
Pages : 418
Book Description
Fault-Tolerant Systems, Second Edition, is the first book on fault tolerance design utilizing a systems approach to both hardware and software. No other text takes this approach or offers the comprehensive and up-to-date treatment that Koren and Krishna provide. The book comprehensively covers the design of fault-tolerant hardware and software, use of fault-tolerance techniques to improve manufacturing yields, and design and analysis of networks. Incorporating case studies that highlight more than ten different computer systems with fault-tolerance techniques implemented in their design, the book includes critical material on methods to protect against threats to encryption subsystems used for security purposes. The text's updated content will help students and practitioners in electrical and computer engineering and computer science learn how to design reliable computing systems, and how to analyze fault-tolerant computing systems. - Delivers the first book on fault tolerance design with a systems approach - Offers comprehensive coverage of both hardware and software fault tolerance, as well as information and time redundancy - Features fully updated content plus new chapters on failure mechanisms and fault-tolerance in cyber-physical systems - Provides a complete ancillary package, including an on-line solutions manual for instructors and PowerPoint slides
Proceedings
Author:
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 372
Book Description
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 372
Book Description
Defect and Fault Tolerance in VLSI Systems
Author: Robert Aitken
Publisher:
ISBN: 9780769522418
Category : Technology & Engineering
Languages : en
Pages : 524
Book Description
DFT 2004 showcases the latest research results in the in the field of defect and fault tolerance in VLSI systems. Its papers cover yield, defect and fault tolerance, error correction, and circuit/system reliability and dependability.
Publisher:
ISBN: 9780769522418
Category : Technology & Engineering
Languages : en
Pages : 524
Book Description
DFT 2004 showcases the latest research results in the in the field of defect and fault tolerance in VLSI systems. Its papers cover yield, defect and fault tolerance, error correction, and circuit/system reliability and dependability.
Fault Tolerant Computer Architecture
Author: Daniel Sorin
Publisher: Springer Nature
ISBN: 3031017234
Category : Technology & Engineering
Languages : en
Pages : 103
Book Description
For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future
Publisher: Springer Nature
ISBN: 3031017234
Category : Technology & Engineering
Languages : en
Pages : 103
Book Description
For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future
2001 International Workshop on System-Level Interconnect Prediction
Author:
Publisher:
ISBN:
Category : Computer architecture
Languages : en
Pages : 220
Book Description
"The SLIP workshop is a forum for the exchange of ideas at the interface between interconnect technology and physical design ... This year, in recognition of the highly diverse backgrounds and motivations of the attendees, SLIP 2001 has been organized around three mini-tutorials: a review of wire distribution models, a look under the hood of a variety of system level interconnect modeling programs, and back end of line yield modeling. These tutorials set the scene for the paper sessions that follow."--Forward.
Publisher:
ISBN:
Category : Computer architecture
Languages : en
Pages : 220
Book Description
"The SLIP workshop is a forum for the exchange of ideas at the interface between interconnect technology and physical design ... This year, in recognition of the highly diverse backgrounds and motivations of the attendees, SLIP 2001 has been organized around three mini-tutorials: a review of wire distribution models, a look under the hood of a variety of system level interconnect modeling programs, and back end of line yield modeling. These tutorials set the scene for the paper sessions that follow."--Forward.
Proceedings of the Estonian Academy of Sciences, Engineering
Software-Implemented Hardware Fault Tolerance
Author: Olga Goloubeva
Publisher: Springer Science & Business Media
ISBN: 0387329374
Category : Technology & Engineering
Languages : en
Pages : 238
Book Description
This book presents the theory behind software-implemented hardware fault tolerance, as well as the practical aspects needed to put it to work on real examples. By evaluating accurately the advantages and disadvantages of the already available approaches, the book provides a guide to developers willing to adopt software-implemented hardware fault tolerance in their applications. Moreover, the book identifies open issues for researchers willing to improve the already available techniques.
Publisher: Springer Science & Business Media
ISBN: 0387329374
Category : Technology & Engineering
Languages : en
Pages : 238
Book Description
This book presents the theory behind software-implemented hardware fault tolerance, as well as the practical aspects needed to put it to work on real examples. By evaluating accurately the advantages and disadvantages of the already available approaches, the book provides a guide to developers willing to adopt software-implemented hardware fault tolerance in their applications. Moreover, the book identifies open issues for researchers willing to improve the already available techniques.
Proceedings of the International Conference on Computational Intelligence and Sustainable Technologies
Author: Kedar Nath Das
Publisher: Springer Nature
ISBN: 9811668930
Category : Technology & Engineering
Languages : en
Pages : 758
Book Description
This book presents the collection of the accepted research papers presented in the 1st ‘International Conference on Computational Intelligence and Sustainable Technologies (ICoCIST-2021)’. This edited book contains the articles related to the themes on artificial intelligence in machine learning, big data analysis, soft computing techniques, pattern recognitions, sustainable infrastructural development, sustainable grid computing and innovative technology for societal development, renewable energy, and innovations in Internet of Things (IoT).
Publisher: Springer Nature
ISBN: 9811668930
Category : Technology & Engineering
Languages : en
Pages : 758
Book Description
This book presents the collection of the accepted research papers presented in the 1st ‘International Conference on Computational Intelligence and Sustainable Technologies (ICoCIST-2021)’. This edited book contains the articles related to the themes on artificial intelligence in machine learning, big data analysis, soft computing techniques, pattern recognitions, sustainable infrastructural development, sustainable grid computing and innovative technology for societal development, renewable energy, and innovations in Internet of Things (IoT).
ISTFA 2006
Author: Electronic Device Failure Analysis Society
Publisher: ASM International
ISBN: 1615030891
Category : Technology & Engineering
Languages : en
Pages : 524
Book Description
Publisher: ASM International
ISBN: 1615030891
Category : Technology & Engineering
Languages : en
Pages : 524
Book Description
Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design
Author: Xiaowei Li
Publisher: Springer Nature
ISBN: 9811985510
Category : Computers
Languages : en
Pages : 318
Book Description
With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.
Publisher: Springer Nature
ISBN: 9811985510
Category : Computers
Languages : en
Pages : 318
Book Description
With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.