Predictable Platforms for Safety-critical Embedded Systems PDF Download

Author: Sidharta Andalam
Publisher:
ISBN:
Category : C (Computer program language)
Languages : en
Pages : 215

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Book Description
Safety-critical embedded systems, commonly found in automotive, space, and health-care, are highly reactive and concurrent. Their most important characteristics are that they require both functional and timing correctness. C has been the language of choice for programming such systems. However, C lacks many features that can make the design process of such systems seamless while also maintaining predictability. In contrast, the synchronous programming paradigm offers an alternative approach for programming safety-critical applications. The formal semantics of synchronous programming languages establish a well-defined behaviour of a program. The synchronous paradigm adopts an abstract notion of time by viewing a system as evolving in a sequence of discrete steps. This simplifies program debugging, testing and validation, and leads to clear temporal constructs. These features make synchronous languages more expressive, but also makes them less familiar to programmers trained in conventional languages, like C. In this thesis, we address the need for a C-based design framework for programming safety-critical applications. Inspired by the synchronous programming paradigm, we propose the following. (1) A new language called, Precision Timed C (PRET-C) that provides a small set of extensions to a subset of C to facilitate effective concurrent programming of safety-critical applications. We present a new synchronous semantics for PRET-C and guarantee that all PRET-C programs are deterministic, reactive, and provides thread-safe communication via shared memory access. (2) A new predictable architecture, called ARPRET. It offers the ability to design time predictable architectures through simple customizations of soft-core processors. We have designed ARPRET particularly for efficient and predictable execution of PRET-C. (3) A new static timing analyser for validating the timing deadlines of a synchronous program. Here, we consider pruning of infeasible paths for tighter analysis along with new fast and precise technique for analysing cache-based architectures. (4) A new cache analysis approach for analysing the behaviour of instructions exe-cuting on a direct mapped cache. Using a binary representation and a new abstraction, we reduce the analysis time without sacrificing the precision. This offers the ability to analyse large PRET-C programs. The proposed framework in this thesis is implemented and evaluated as follows. Firstly, the PRET-C language is supported using C macros. Experimental results reveal that PRET-C yields significantly more efficient code compared to other C-based synchronous languages. Secondly, the ARPRET architecture is synthesised on an FPGA and it is shown through extensive benchmarking that this significantly improves throughput of PRET-C programs, while maintaining predictability. Thirdly, the proposed static timing analyser is based on the model checking technique. It is very effective in pruning infeasible paths. Experiments show that the proposed approach gives significantly more precise results than the current state-of-the-art static timing analysers for synchronous programs. Finally, the proposed cache analysis approach is very precise and completes within a reasonable amount of time. This is unlike the existing cache analysing approaches where either precision or scalability (analysis time) is sacrificed. Overall, results demonstrate the viability of the ideas presented in this thesis for the development and verification of large safety-critical applications.