Author: Kishore K. RaoPublisher:
ISBN:
Category :
Languages : en
Pages : 242
Book Description
Performance Analysis of a High-speed Packet Switching Architecture for BISDN and Its Applicability to SONET
Author: Kishore K. RaoMasters Theses in the Pure and Applied Sciences
Author: Wade H. ShaferPublisher: Springer Science & Business Media
ISBN: 1461524539
Category : Science
Languages : en
Pages : 391
Book Description
Masters Theses in the Pure and Applied Sciences was first conceived, published, and disseminated by the Center for Information and Numerical Data Analysis and Synthesis (CINDAS)* at Purdue University in 1957, starting its coverage of theses with the academic year 1955. Beginning with Volume 13, the printing and dis semination phases of the activity were transferred to University Microfilms/Xerox of Ann Arbor, Michigan, with the though that such an arrangement would be more beneficial to the academic and general scientific and technical community. After five years of this joint undertaking we had concluded that it was in the interest of all concerned if the printing and distribution of the volumes were handled by an international publishing house to assure improved service and broader dissemi nation. Hence, starting with Volume 18, Masters Theses in the Pure and Applied Sciences has been disseminated on a worldwide basis by Plenum Publishing Corporation of New York, and in the same year the coverage was broadened to include Canadian universities. All back issues can also be ordered from Plenum. We have reported in Volume 37 (thesis year 1992) a total of 12,549 thesis titles from 25 Canadian and 153 United States universities. We are sure that this broader base for these titles reported will greatly enhance the value of this impor tant annual reference work. While Volume 37 reports theses submitted in 1992, on occasion, certain uni versities do report theses submitted in previous years but not reported at the time.
Performance Evaluation and High Speed Switching Fabrics and Networks
Author: Thomas G. RobertazziPublisher: Wiley-IEEE Press
ISBN:
Category : Computers
Languages : en
Pages : 488
Book Description
A handy source for practicing engineers and researchers, this book offers collected examples of successful performance evaluation of high speed telecommunications switching fabrics such as ATM networks and high speed interconnection technology for computers. It emphasizes the performance evaluation of such switches as they apply to predicting a proposed system's performance through the use of statistical models -- a cost-saving way for communications engineers to test the design of a system without having to construct it.
Performance Analysis of a Very Fast Packet Switching System for Broadband ISDN
Author: Radha N. S. RaoPublisher:
ISBN:
Category : Broadband communication systems
Languages : en
Pages : 148
Book Description
Masters Theses in the Pure and Applied Sciences
Author: W. H. ShaferPublisher: Springer Science & Business Media
ISBN: 9780306447112
Category : Education
Languages : en
Pages : 410
Book Description
Volume 37 (thesis year 1992) reports a total of 12,549 thesis titles from 25 Canadian and 153 US universities (theses submitted in previous years but only now reported are indicated by the thesis year shown in parenthesis). The organization, like that of past years, consists of thesis titles arrange
High-performance Packet Switching Architectures
Author: Itamar ElhananyPublisher: Springer Science & Business Media
ISBN: 1846282748
Category : Technology & Engineering
Languages : en
Pages : 239
Book Description
Internet traffic is increasing by at least 200% per year and this is the first book to report on the current state-of-the-art of packet-switching architectures. The book to covers the subject in a comprehensive survey and presents contributions from the leading researchers in industry and universities. A mix of theoretical and practical material makes this book an essential reference for researchers in academia as well as industrial engineers.
Analysis of Novel High-performance Switch Architectures for Broadband-ISDN.
Author: Anil Kumar GuptaPublisher:
ISBN:
Category : Broadband communication systems
Languages : en
Pages : 276
Book Description
In this thesis, we present an analysis of three novel switch architectures for Broadband-ISDN using the Asynchronous Transfer Mode (ATM). Our focus is on high-performance switch architectures, which have low to medium hardware complexity.
On-board B-ISDN Fast Packet Switching Architectures. Phase 2: Development. Proof-of-concept Architecture Definition Report
Author: On-board B-ISDN Fast Packet Switching Architectures. Phase 1: Study
Author: Modeling and Analysis of Packet Switch Architectures for Broadband ISDN.
Author: Ibrahim Issa MakhamrehPublisher:
ISBN:
Category :
Languages : en
Pages : 0
Book Description
In this thesis we analyze broadband switching architectures based on the Asynchronous Transfer Mode (ATM). Many architectures have been proposed in the literature for high-speed packet switches. We first review some of these switch architectures and their performance. The high-performance switch architectures, in general, require that the buffers be placed at the output ports. These output buffered switches tend to have large hardware complexity or require high speedup in their operation. Our focus is on high-performance switch architectures with low speedup output buffers or a shared buffer. An N $\times$ d ATM switch with finite output buffers is modeled as a discrete-time queue. The case d = 1 represents an ATM multiplexer with N input source and a finite capacity buffer. Loading at the input as well as at the output is considered to be imbalanced, which greatly affects the switch performance especially the hot spot traffic pattern. We also consider the switch with reduced speedup. In this case, the number of cells going to an output buffer in one time slot is limited to L N. This greatly simplifies the implementation of the switch. The arrivals to an input port of the switch, besides being bursty, are correlated in the sense that a burst arriving to an output port brings with it several cells belonging to the same virtual connection. As a worst case, we assume that consecutive cells in a burst are heading to the same output port. This greatly affects the dimensioning of the switch buffer. The input process to each input port is modeled by an Interrupted Bernoulli Process (IBP). We have developed an aggregation technique which allows the reduction of the state space that describes the arrival processes to the switch. This makes handling the output buffer driven by the induced process more manageable. Traffic priorities in ATM networks is an important issue because such networks will support applications with diverse traffic characteristics. In the light of this, we consider traffic priorities in an output buffered switch and in a completely shared-buffer switch. The transient analysis of the output buffer is also studied by considering the mean time until buffer overflow. The switch architecture that has the maximum mean-time-to-blocking is favorable. The busy period of the output buffer is also characterized. In routing the whole burst to an output buffer, the output process becomes more bursty than the input process.