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Author: University of Illinois at Urbana-Champaign. Center for Reliable and High-Performance Computing Publisher: ISBN: Category : Languages : en Pages : 288
Book Description
With increase in complexity of digital circuits, it has become extremely important to detect faults to ensure correct operation of a digital circuit. Since test generation and fault simulation for circuits of VLSI complexity can take a prohibitive amount of time, speeding up test generation and fault simulation algorithms by either using better uniprocessor heuristics or by using the tremendous computing power available on multiprocessors thus becomes important. The design and analysis of parallel algorithms for test generation and fault simulation are the focus of this thesis research. We first categorize various parallel processing techniques available for test generation and fault simulation. We then propose a parallel search method to overcome the deficiencies of inaccurate search heuristics. We show that this method not only results in faster execution of the test generation algorithm but also results in a better quality of the solution. We also propose a performance model to evaluate the parallel search technique. We then propose fault partitioning techniques to speed up test generation for faults which are relatively easy to detect. The objective of the fault partitioning techniques is to maximize concurrency without affecting the quality of the overall solution. We propose load balancing techniques which try to minimize the processor idle time with very low communication overhead. We propose a performance model which takes into account the various trade-offs in exploiting parallelism in a test generation/fault simulation environment. Finally, we present a parallel test generation system for sequential circuits. A parallel search technique is used to accelerate test generation for hard to detect faults, and a circuit partitioned approach is used to accelerate fault simulation.
Author: University of Illinois at Urbana-Champaign. Center for Reliable and High-Performance Computing Publisher: ISBN: Category : Languages : en Pages : 288
Book Description
With increase in complexity of digital circuits, it has become extremely important to detect faults to ensure correct operation of a digital circuit. Since test generation and fault simulation for circuits of VLSI complexity can take a prohibitive amount of time, speeding up test generation and fault simulation algorithms by either using better uniprocessor heuristics or by using the tremendous computing power available on multiprocessors thus becomes important. The design and analysis of parallel algorithms for test generation and fault simulation are the focus of this thesis research. We first categorize various parallel processing techniques available for test generation and fault simulation. We then propose a parallel search method to overcome the deficiencies of inaccurate search heuristics. We show that this method not only results in faster execution of the test generation algorithm but also results in a better quality of the solution. We also propose a performance model to evaluate the parallel search technique. We then propose fault partitioning techniques to speed up test generation for faults which are relatively easy to detect. The objective of the fault partitioning techniques is to maximize concurrency without affecting the quality of the overall solution. We propose load balancing techniques which try to minimize the processor idle time with very low communication overhead. We propose a performance model which takes into account the various trade-offs in exploiting parallelism in a test generation/fault simulation environment. Finally, we present a parallel test generation system for sequential circuits. A parallel search technique is used to accelerate test generation for hard to detect faults, and a circuit partitioned approach is used to accelerate fault simulation.
Author: F. Lombardi Publisher: Springer Science & Business Media ISBN: 9400914172 Category : Technology & Engineering Languages : en Pages : 531
Book Description
This volume contains a collection of papers presented at the NATO Advanced Study Institute on ·Testing and Diagnosis of VLSI and ULSI" held at Villa Olmo, Como (Italy) June 22 -July 3,1987. High Density technologies such as Very-Large Scale Integration (VLSI), Wafer Scale Integration (WSI) and the not-so-far promises of Ultra-Large Scale Integration (ULSI), have exasperated the problema associated with the testing and diagnosis of these devices and systema. Traditional techniques are fast becoming obsolete due to unique requirements such as limited controllability and observability, increasing execution complexity for test vector generation and high cost of fault simulation, to mention just a few. New approaches are imperative to achieve the highly sought goal of the • three months· turn around cycle time for a state-of-the-art computer chip. The importance of testing and diagnostic processes is of primary importance if costs must be kept at acceptable levels. The objective of this NATO-ASI was to present, analyze and discuss the various facets of testing and diagnosis with respect to both theory and practice. The contents of this volume reflect the diversity of approaches currently available to reduce test and diagnosis time. These approaches are described in a concise, yet clear way by renowned experts of the field. Their contributions are aimed at a wide readership: the uninitiated researcher will find the tutorial chapters very rewarding. The expert wiII be introduced to advanced techniques in a very comprehensive manner.
Author: International Business Machines Corporation. Research Division Publisher: ISBN: Category : Parallel processing (Electronic computers) Languages : en Pages : 16
Author: Arrems Hua Publisher: Springer Science & Business Media ISBN: 3642030947 Category : Computers Languages : en Pages : 896
Book Description
This book constitutes the refereed proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2009, held in Taipei, Taiwan, in June 2009. The 80 revised full papers were carefully reviewed and selected from 243 submissions. The papers are organized in topical sections on bioinformatics in parallel computing; cluster, grid and fault-tolerant computing; cluster distributed parallel operating systems; dependability issues in computer networks and communications; dependability issues in distributed and parallel systems; distributed scheduling and load balancing, industrial applications; information security internet; multi-core programming software tools; multimedia in parallel computing; parallel distributed databases; parallel algorithms; parallel architectures; parallel IO systems and storage systems; performance of parallel ditributed computing systems; scientific applications; self-healing, self-protecting and fault-tolerant systems; tools and environments for parallel and distributed software development; and Web service.
Author: Wai-Kai Chen Publisher: CRC Press ISBN: 9781420041408 Category : Computers Languages : en Pages : 3076
Book Description
A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-
Author: Sunil P Khatri Publisher: Springer Science & Business Media ISBN: 1441909443 Category : Technology & Engineering Languages : en Pages : 207
Book Description
Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications which are used in key time-consuming steps of the VLSI design ?ow. Further, these applications also have different degrees of inherent parallelism in them. We study both control-dominated EDA applications and control plus data parallel EDA applications. We accelerate these applications on these different hardware platforms. We also present an automated approach for accelerating certain uniprocessor applications on a graphics processor. This monograph compares custom ICs, FPGAs, and graphics processing units (GPUs) as potential platforms to accelerate EDA algorithms. It also provides details of the programming model used for interfacing with the GPUs.
Author: Afonso Ferreira Publisher: Springer Science & Business Media ISBN: 9783540615491 Category : Computers Languages : en Pages : 772
Book Description
This book constitutes the refereed proceedings of the Third International Workshop on Parallel Algorithms for Irregularly Structured Problems, IRREGULAR '96, held in Santa Barbara, California, in August 1996. The volume presents 28 revised full papers selected from 51 submissions; also included are one full invited paper by Torben Hagerup and abstracts of four other invited talks. The papers are organized in topical sections on sparse matrix problems, partitioning and domain composition, irregular applications, communication and synchronization, systems support, and mapping and load balancing.
Author: Wade H. Shafer Publisher: Springer Science & Business Media ISBN: 1461519691 Category : Science Languages : en Pages : 426
Book Description
Masters Theses in the Pure and Applied Sciences was first conceived, published, and disseminated by the Center for Information and Numerical Data Analysis and Synthesis (CINDAS)* at Purdue University in 1957, starting its coverage of theses with the academic year 1955. Beginning with Volume 13, the printing and dis semination phases of the activity were transferred to University Microfilms/Xerox of Ann Arbor, Michigan, with the thought that such an arrangement would be more beneficial to the academic and general scientific and technical community. After five years of this joint undertaking we had concluded that it was in the interest of all concerned if the printing and distribution of the volumes were handled by an international publishing house to assure improved service and broader dissemination. Hence, starting with Volume 18, Masters Theses in the Pure and Applied Sciences has been disseminated on a worldwide basis by Plenum Publishing Corporation of New York, and in the same year the coverage was broadened to include Canadian universities. All back issues can also be ordered from Plenum. We have reported in Volume 38 (thesis year 1993) a total of 13,787 thesis titles from 22 Canadian and 164 United States universities. We are sure that this broader base for these titles reported will greatly enhance the value of this impor tant annual reference work. While Volume 38 reports theses submitted in 1993, on occasion, certain uni versities do report theses submitted in previous years but not reported at the time.
Author: University of Illinois at Urbana-Champaign. Center for Reliable and High-Performance Computing
Author: University of Illinois at Urbana-Champaign. Center for Reliable and High-Performance Computing
Author: Dilip Krishnaswamy
Author: F. Lombardi
Author: International Business Machines Corporation. Research Division
Author: Arrems Hua
Author: Wai-Kai Chen
Author: Sunil P Khatri
Author: Afonso Ferreira
Author: Carlos R. P. Hartmann
Author: Wade H. Shafer