Author: Dilip KrishnaswamyPublisher:
ISBN:
Category :
Languages : en
Pages : 220
Book Description
Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
Author: Dilip KrishnaswamyParallel Algorithms for Test Generation and Fault Simulation
Author: University of Illinois at Urbana-Champaign. Center for Reliable and High-Performance ComputingPublisher:
ISBN:
Category :
Languages : en
Pages : 288
Book Description
With increase in complexity of digital circuits, it has become extremely important to detect faults to ensure correct operation of a digital circuit. Since test generation and fault simulation for circuits of VLSI complexity can take a prohibitive amount of time, speeding up test generation and fault simulation algorithms by either using better uniprocessor heuristics or by using the tremendous computing power available on multiprocessors thus becomes important. The design and analysis of parallel algorithms for test generation and fault simulation are the focus of this thesis research. We first categorize various parallel processing techniques available for test generation and fault simulation. We then propose a parallel search method to overcome the deficiencies of inaccurate search heuristics. We show that this method not only results in faster execution of the test generation algorithm but also results in a better quality of the solution. We also propose a performance model to evaluate the parallel search technique. We then propose fault partitioning techniques to speed up test generation for faults which are relatively easy to detect. The objective of the fault partitioning techniques is to maximize concurrency without affecting the quality of the overall solution. We propose load balancing techniques which try to minimize the processor idle time with very low communication overhead. We propose a performance model which takes into account the various trade-offs in exploiting parallelism in a test generation/fault simulation environment. Finally, we present a parallel test generation system for sequential circuits. A parallel search technique is used to accelerate test generation for hard to detect faults, and a circuit partitioned approach is used to accelerate fault simulation.
Data Parallel Fault Simulation for Combinational and Sequential Circuits
Author: Minesh Balkrishan AminPublisher:
ISBN:
Category :
Languages : en
Pages : 264
Book Description
Sequential Circuit Test Pattern Generation Using Empirical Partial Scan and Distributed Computation
Author: Kee Sup KimTest Generation for Digital Circuits Using Parallel Processing
Author: Carlos R. P. HartmannPublisher:
ISBN:
Category :
Languages : en
Pages : 64
Book Description
Testing of Digital Systems
Author: N. K. JhaPublisher: Cambridge University Press
ISBN: 9781139437431
Category : Computers
Languages : en
Pages : 1022
Book Description
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Time Efficient Automatic Test Pattern Generation Systems
Author: Byungse SoSequential Logic Testing and Verification
Author: Abhijit GhoshPublisher: Springer Science & Business Media
ISBN: 1461536464
Category : Technology & Engineering
Languages : en
Pages : 224
Book Description
In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance.
A Study of Automatic Test Pattern Generation Systems
Author: Kyuchull KimAdvanced Techniques for Embedded Systems Design and Test
Author: Juan C. LópezPublisher: Springer Science & Business Media
ISBN: 1475744196
Category : Computers
Languages : en
Pages : 298
Book Description
As electronic technology reaches the point where complex systems can be integrated on a single chip, and higher degrees of performance can be achieved at lower costs, designers must devise new ways to undertake the laborious task of coping with the numerous, and non-trivial, problems that arise during the conception of such systems. On the other hand, shorter design cycles (so that electronic products can fit into shrinking market windows) put companies, and consequently designers, under pressure in a race to obtain reliable products in the minimum period of time. New methodologies, supported by automation and abstraction, have appeared which have been crucial in making it possible for system designers to take over the traditional electronic design process and embedded systems is one of the fields that these methodologies are mainly targeting. The inherent complexity of these systems, with hardware and software components that usually execute concurrently, and the very tight cost and performance constraints, make them specially suitable to introduce higher levels of abstraction and automation, so as to allow the designer to better tackle the many problems that appear during their design. Advanced Techniques for Embedded Systems Design and Test is a comprehensive book presenting recent developments in methodologies and tools for the specification, synthesis, verification, and test of embedded systems, characterized by the use of high-level languages as a road to productivity. Each specific part of the design process, from specification through to test, is looked at with a constant emphasis on behavioral methodologies. Advanced Techniques for Embedded Systems Design and Test is essential reading for all researchers in the design and test communities as well as system designers and CAD tools developers.