Author: Sriram BalasubramanianPublisher:
ISBN:
Category :
Languages : en
Pages : 376
Book Description
Nanoscale Thin-body MOSFET Design and Applications
Author: Sriram BalasubramanianPublisher:
ISBN:
Category :
Languages : en
Pages : 376
Book Description
Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs
Author: Jerry G. FossumPublisher: Cambridge University Press
ISBN: 1107434491
Category : Technology & Engineering
Languages : en
Pages : 227
Book Description
Understand the theory, design and applications of the two principal candidates for the next mainstream semiconductor-industry device with this concise and clear guide to FD/UTB transistors. • Describes FD/SOI MOSFETs and 3-D FinFETs in detail • Covers short-channel effects, quantum-mechanical effects, applications of UTB devices to floating-body DRAM and conventional SRAM • Provides design criteria for nanoscale FinFET and nanoscale thin- and thick-BOX planar FD/SOI MOSFET to help reduce technology development time • Projects potential nanoscale UTB CMOS performances • Contains end-of-chapter exercises. For professional engineers in the CMOS IC field who need to know about optimal non-classical device design and integration, this is a must-have resource.
Advanced Nanoscale MOSFET Architectures
Author: Kalyan BiswasPublisher: John Wiley & Sons
ISBN: 1394188951
Category : Technology & Engineering
Languages : en
Pages : 340
Book Description
Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs. Additional topics covered include: High-k gate dielectrics and metal gate electrodes for multi-gate MOSFETs, covering gate stack processing and metal gate modification Strain engineering in 3D complementary metal-oxide semiconductors (CMOS) and its scaling impact, and strain engineering in silicon–germanium (SiGe) FinFET and its challenges and future perspectives TCAD simulation of multi-gate MOSFET, covering model calibration and device performance for analog and RF applications Description of the design of an analog amplifier circuit using digital CMOS technology of SCL for ultra-low power VLSI applications Advanced Nanoscale MOSFET Architectures helps readers understand device physics and design of new structures and material compositions, making it an important resource for the researchers and professionals who are carrying out research in the field, along with students in related programs of study.
Nanoscale Ultra-thin-body Silicon-on-insulator MOSFET with a SiGe/Si Heterostructure Channel
Author: Yee-Chia YeoEvolutionary MOSFET Structure and Channel Design for Nanoscale CMOS Technology
Author: Byron HoPublisher:
ISBN:
Category :
Languages : en
Pages : 198
Book Description
The constant pace of CMOS technology scaling has enabled continuous improvement in integrated-circuit cost and functionality, generating a new paradigm shift towards mobile computing. However, as the MOSFET dimensions are scaled below 30nm, electrostatic integrity and device variability become harder to control, degrading circuit performance. In order to overcome these issues, device engineers have started transitioning from the conventional planar bulk MOSFET toward revolutionary thin-body transistor structures such as the FinFET or fully-depleted silicon-on-insulator (FDSOI) MOSFET. While these alternatives appear to be elegant solutions, they require increased process complexity and/or more expensive starting substrates, making development and manufacturing costs a concern. For certain applications (such as mobile electronics), cost is still an important factor, inhibiting the quick adoption of the FinFET and FDSOI MOSFET structures while providing an opportunity to extend the competitiveness of planar bulk-silicon CMOS. A segmented-channel MOSFET (SegFET) design, which combines the benefits of both planar bulk MOSFETs (i.e. lower process complexity and/or cost) and thin-body transistor structures (i.e. improved electrostatic integrity), can provide an evolutionary pathway to enable the continued scaling of planar bulk technology below 20nm. In this work, experimental results comparing SegFETs and planar MOSFETs show suppressed short-channel effects and comparable on-state current (despite halving the effective device width). In addition, three-dimensional device simulations were used to optimize and benchmark the bulk SegFET and FinFET designs. Compared to the FinFET design, the results indicate that the SegFET can achieve similar on-state current performance and intrinsic delay (for the same channel stripe pitch) at a lower height/width aspect ratio and less aggressive retrograde channel doping gradient for improved manufacturability, making it a promising candidate for continued bulk-silicon CMOS transistor scaling. High-mobility channels are also investigated in this work for their potential to improve MOSFET performance, but issues with physical material parameters (electrostatic control, strain effects, etc.) and process integration necessitate careful design when implementing these materials in the MOSFET channel regions. Because germanium (Ge) and silicon-germanium (Si1-xGex) alloys are Group IV materials like silicon (Si), and since these materials are already extensively used in mainstream volume integrated-circuit manufacturing, they represent the most straightforward path to integrating high-mobility channels on silicon. Device simulations are used to optimize Si1-xGex channel thickness and Ge concentration for Si1-xGex/Si heterostructure p-channel MOSFETs; it is found that a thin (
Advanced Source/drain and Contact Design for Nanoscale CMOS
Author: Reinaldo A. VegaNanoscale MOS Transistors
Author: David EsseniPublisher: Cambridge University Press
ISBN: 1139494384
Category : Technology & Engineering
Languages : en
Pages : 489
Book Description
Written from an engineering standpoint, this book provides the theoretical background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOS nanoscale transistors. A wealth of applications, illustrations and examples connect the methods described to all the latest issues in nanoscale MOSFET design. Key areas covered include: • Transport in arbitrary crystal orientations and strain conditions, and new channel and gate stack materials • All the relevant transport regimes, ranging from low field mobility to quasi-ballistic transport, described using a single modeling framework • Predictive capabilities of device models, discussed with systematic comparisons to experimental results
Nanometer CMOS
Author: Juin J. LiouPublisher: CRC Press
ISBN: 1000045242
Category : Science
Languages : en
Pages : 251
Book Description
This book presents the material necessary for understanding the physics, operation, design, and performance of modern MOSFETs with nanometer dimensions. It offers a brief introduction to the field and a thorough overview of MOSFET physics, detailing the relevant basics. The authors apply presented models to calculate and demonstrate transistor characteristics, and they include required input data (e.g., dimensions, doping) enabling readers to repeat the calculations and compare their results. The book introduces conventional and novel advanced MOSFET concepts, such as multiple-gate structures or alternative channel materials. Other topics covered include high-k dielectrics and mobility enhancement techniques, MOSFETs for RF (radio frequency) applications, MOSFET fabrication technology.
Nanoscale Thin-body CMOS Devices
Author: Leland ChangPhysics and Design of Nonclassical Nanoscale CMOS Devices with Ultra-thin Bodies
Author: Vishal P. TrivediPublisher:
ISBN:
Category : Metal oxide semiconductor field-effect transistors
Languages : en
Pages :
Book Description
Thus, the impact of undoped body on the electrostatics of the generic DG MOSFET is examined. Carrier distribution in the body and in the quantized energy states is found to have profound effects in both weak and strong inversion. Quantum-mechanical (QM) effects, dependent on t sub Si, transverse electric field (epsilon sub x), and crystal orientation, are also physically modeled. With an undoped UTB, the need for gate-source/drain (G-S/D) underlap is emphasized as the gate length (L sub gate) approaches 7nm. L sub eff is related to L sub gate for designs with G-S/D underlap. Using numerical device simulations, physical insights on the bias dependence and the S/D lateral doping profile dependence of L sub eff are gained, relating the noted scalability in terms of L sub eff to L sub gate. The extrinsic S/D series resistance (R sub S/D) and the parasitic G-S/D capacitance (C sub GS/D) are also examined.