Author: Sudheer VootkuriPublisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 168
Book Description
Modeling Independent-double-gate Silicon-on-insulator (IDG SOI) MOSFET
Author: Sudheer VootkuriPublisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 168
Book Description
The modeling of silicon-on-insulator (SOI) MOSFETs for numerical simulation
Author: Susan Marie GreenSilicon-on-insulator Technology and Devices XI
Author: Electrochemical Society. MeetingPublisher: The Electrochemical Society
ISBN: 9781566773751
Category : Science
Languages : en
Pages : 538
Book Description
Modeling of Characteristics of Fully Depleted Sub-half-micron Silicon-on-insulator (SOI) MOSFET's
Author: Tommy Chi-wen HsiaoCompact Modelling of DGMOSFET's
Author: Neha AgarwalPublisher: LAP Lambert Academic Publishing
ISBN: 9783659246876
Category :
Languages : en
Pages : 56
Book Description
Double gate MOSFET is widely used for sub-50nm technology of transistor design .They have immunity to short channel effects, reduced leakage current and high scaling potential. The single gate Silicon-on-insulator (SOI) devices give improved circuit speed and power consumption .But as the transistor size is reduced the close proximity between source and drain reduces the ability of the gate electrode to control the flow of current and potential distribution in the channel. To reduce SCE we need increase gate to channel coupling with respect to source/drain to channel coupling. This book presents the compact modeling of long channel undoped and doped symmetric double-gate MOSFET. The formulation starts with the solution of Poisson's equation which is then coupled to the Pao-Sah current equation to obtain the analytical drain-current model in terms of carrier concentration. The performance analysis of both the doped and undoped body symmetric DGMOS is done by using the model . Comparison of the two types of DGMOS is also done on the basis their electrical characteristics.
Modeling and SPICE Implementation of Silicon-on-insulator (SOI) Four Gate (G4FET) Transistor
Author: Md Sakib HasanPublisher:
ISBN:
Category : Electronic circuit design
Languages : en
Pages : 183
Book Description
As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal-oxide-semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET.
Physics Based Mdeling of Multiple Gate Transistors on Silicon-on-Insulator (SOI)
Author: Publisher:
ISBN:
Category :
Languages : en
Pages : 153
Book Description
G4FET is a novel device built on Silicon-on-Isulator (SOI). Due to the presence of Bulk-Si, it is impossible to have more than one gate for each transistor in conventional process technology. However, it is possible to have multiple gates for each transistor in SOI devices due to the presence of buried oxide, which can be used as an independent gate. Besides the oxide gates, junction gates can also be introduced. Due to the presence of the thin active layer, the junction gate can reach to the bottom and can be used to isolate and control the conduction in the transistors. As a result, the maximum number of gates that can be achieved in SOI is four. A transistor with four gates is called G4FET. G4FET offers all the features of SOI technology. It offers remedies of the drawbacks of Bulk-Si technology. The operation of the multiple gates has applications for mixed-signal circuits, quantum wire, and single transistor multiple gates logic schemes, etc. The research goal is to understand the device physics of G4FET. Understanding device physics will provide enough information to set device parameters to optimize device performances. The operation of semiconductor devices depends on several material parameters, device dimensions and structure. The objective of this research is to develop a model that includes material parameters, device dimensions and structure. The second objective of this research is to develop a numerical model from available data. The numerical model is useful for circuit simulation of G4FET, which provides information about the characteristics of G4FET, when used as a circuit element.
An Analysis on the Simulation of the Leakage Currents of Independent Double Gate SOI MOSFET Transistors
Author: Himaja Reddy MoolamallaPublisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 174
Book Description
A General Physical Model for Double-gate SOI MOSFETs
Author: Zheming LiDesign, Simulation and Analysis of the Switching and RF Performance of Multi-gate Silicon-on-insulator Mosfet Device Structures
Author: Aniket A. BreedPublisher:
ISBN:
Category :
Languages : en
Pages : 362
Book Description
Silicon-only MOSFETs have fast approached their scaling limitations and new technologies are constantly being investigated with an intention to replace the planar silicon-only MOSFET. The Silicon-on-Insulator (SOI) technology is the forerunner in many such ongoing investigations. Devices fabricated using this technology exhibit reduced junction capacitances, lower leakage currents and higher ease of integration when scaled into the sub-nanometer regime. With the advent of novel and reliable fabrication techniques, multi-gate SOI devices viz. the FinFET, TriGate, Omega-gate and Quadruple gate MOSFETs are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. This study examines the switching and RF performance of these multi-gate devices under aggressive scaling conditions with the aid of three dimensional numerical simulations. The primary focus of investigation is a variation in the subthreshold device performance when subjected to a change in dimensions. Also investigated are the effects of variation in the lengths of the extension and LDD regions on the subthreshold device performance of these multi-gate MOSFETS. The study also includes an analysis of the subthreshold behavior under high temperature conditions. Most importantly, this study investigates the microwave performance of the devices via a simulation analysis of their small-signal behavior. The variation in the microwave performance of these devices is further extended to include the effects of variation in the length of the extension regions on the RF device performance. In conjunction with N-channel devices, the study also focuses on P-channel devices and compares the performances of the two. Out of the four multi-gate SOI device structures, the FinFET and the TriGate appear to be the most promising alternatives to replace the conventional MOSFET in future applications.