Author: Iwao YamazakiPublisher:
ISBN:
Category :
Languages : en
Pages : 48
Book Description
Modeling and Diagnosis of Cell Type Faults in Digital Circuits
Author: Iwao YamazakiDiagnosis and Reliable Design of Digital Systems
Author: Melvin A. BreuerPublisher: Computer Science Press, Incorporated
ISBN:
Category : Computers
Languages : en
Pages : 328
Book Description
Considers the problems of test generation, simulation, & reliability-enhancing design techniques for digital circuits & systems.
Model-based Fault Diagnosis of Digital Circuits
Author: Benjamin Rogel FavilaFault Diagnosis of Digital Systems
Author: Herbert Y. ChangPublisher: Krieger Publishing Company
ISBN:
Category : Computers
Languages : en
Pages : 186
Book Description
Fault Detection in Digital Circuits
Author: Arthur D. FriedmanPublisher: Prentice Hall
ISBN:
Category : Computers
Languages : en
Pages : 252
Book Description
Fault Diagnosis in Digital Circuits
Author: Mohamed Saled Soliman MahmoudPublisher:
ISBN: 9780355460582
Category :
Languages : en
Pages :
Book Description
The goals of fault diagnosis are to ascertain whether faults are present in (fault detection) and to identify them (fault location). Fault location is commonly performed with the aid of a fault dictionary. Fault dictionaries are constructed via fault simulation under the single fault assumption. The single fault-model often assumes a circuit is tested often enough such that no more than one physical defect is likely to occur between two consecutive test applications. This strategy is not valid when one physical defect manifests itself as multiple faults. It is observed that the presence of redundant faults also invalidates the frequent testing strategy, since a redundant fault may mask the existence of a detectable fault. In all these situations, a multiple fault model is required. However, in almost all practical cases a fault dictionary for multiple faults is infeasible to generate due to an exponential number of equivalence classes. In this dissertation, we first present a VHDL-based CAD tool that integrates design error injection, simulation, and diagnosis for digital circuits. The tool uses an FPGA-based board to inject error models in the design and compute the error free and erroneous signatures of internal lines. The signatures are later used for detection and diagnosis of errors for the circuit under test (CUT). Several experiments were conducted to demonstrate the capabilities of the tool. The obtained results demonstrate that the tool could detect and locate the source faulty node(s) within the CUT. Then, a new approach for a developed fault diagnosis method. Our approach is based on an enhanced deduction algorithm, which processes the actual response (effect) of CUT, to determine fault situations (causes). The main tool of our approach processes the response to deduce the internal signal values. A multiple stuck at fault model is implicitly employed and no-fault enumeration is required. The enhanced deduction algorithm is applicable to complicated combinational circuits. The internal values obtained are used to determine fault situations in CUT compatible with the applied test T and the response. Our analysis can identify fault locations and values (s-a-0 or s-a-1). Our main result is that any stuck fault can be diagnosed. Preliminary results demonstrate that our technique always achieves great accuracy for detecting and locating the faults, saving a large amount of time, especially for more complicated combinational circuits. The problems solved by our procedure are using deterministic test vectors. We next present a new approach for a developed fault diagnosis method. Our approach is based on an enhanced deduction algorithm and a backtracking strategy which can be regarded as a recursive process of value justification in which we first justify (explain) the values obtained at the primary outputs (POs). To justify a (0) value on the output of a- NAND gate (assuming it is normal), we need all the gate inputs to be (1). To justify a (1) value we need at least one input to have value (0). All the known values of internal normal lines must be justified by values of their predecessors. When both 0 and 1 values have been deduced for a gate output and it is critical, it is identified as normal and all its currently known values are analyzed. In some cases, we need to decide to select one of the possible ways to justify a (1) value on the output of a- NAND gate. If a decision leads to an inconsistency (self-contradictory state) with the forward propagated value, the algorithm will backtrack to the last decision point and try an alternative decision. After a decision is made, all the implications resulting from that decision are performed. If no inconsistency is detected, a new decision point is necessary. Otherwise, a solution has been obtained. A solution is a set of values which could have occurred in the CUT, that is, a possible set of actual values. The main tool of our approach processes the response to deduce the internal signal values in all possible solutions.
Advanced Test Methods for SRAMs
Author: Alberto BosioPublisher: Springer Science & Business Media
ISBN: 1441909389
Category : Technology & Engineering
Languages : en
Pages : 179
Book Description
Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults", are not covered by classical test solutions and require the dedicated test sequences presented in this book.
Fault Diagnosis of Digital Circuits
Author: V. N. YarmolikPublisher: John Wiley & Sons
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 216
Book Description
The continual explosion of computer development has led to inadequate coverage of proper & useful on-line testing techniques. This text fills the gap in the literature by presenting the latest techniques available for digital devices used in the most popular computers. Initial chapters explore the classic problems of on-line testing, pointing out the limited applications of conventional approaches to the problem of diagnosing digital devices using LSI & VLSI chips. Chapters 4-7 cover compact testing methods used to diagnose complex digital circuits. Chapters 8 & 9 analyze the techniques of compressing output responses of a digital circuit, while chapter 10 surveys promising recent signature generation techniques for binary sequences. The final chapter covers multi-output digital circuits.
Assessing Fault Model and Test Quality
Author: Kenneth M. ButlerPublisher: Springer Science & Business Media
ISBN: 1461536065
Category : Computers
Languages : en
Pages : 142
Book Description
For many years, the dominant fault model in automatic test pattern gen eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought.
Author: Mario Lúcio Côrtes