Author: Ping Chin YehPublisher:
ISBN:
Category :
Languages : en
Pages : 334
Book Description
Modeling and Design of Deep-submicron Fully Depleted Silicon-on- Insulator Complementary Metal-oxide-semiconductor for Low-voltage Integrated Circuit Applications
Author: Ping Chin YehModeling and Design of Deep-submicron Fully Depleted Silicon-on-insulator Complementary Metal-oxide-semicondutor for Low-voltage Integrad Circuit Applications
Author: Ping Chin YehChemical Abstracts
Author: American Doctoral Dissertations
Author: Publisher:
ISBN:
Category : Dissertation abstracts
Languages : en
Pages : 872
Book Description
Dissertation Abstracts International
Author: Publisher:
ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 846
Book Description
Modeling and Simulation of the Fully Depleted Silicon-on-insulator Mosfet for Submicron Cmos Ic Design
Author: Jin Young ChoiElectrical & Electronics Abstracts
Author: Publisher:
ISBN:
Category : Electrical engineering
Languages : en
Pages : 1860
Book Description
Modeling and Characterization of Deep Submicron Devices on Fully Depleted Silicon-on-insulator Technology
Author: Srinivasa Rao BannaPublisher:
ISBN:
Category : Silicon-on-insulator technology
Languages : en
Pages : 336
Book Description
Device Design of Sub-100nm Fully-depleted Silicon-on-Insulator (SOI) Devices Based on High-k Epitaxial-Buried Oxide
Author: Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
The Integrated Circuit industry is driven by the continuously shrinking feature size of devices. The era of planar bulk MOS transistor, however, is nearing its end. The performance of bulk MOS transistor is severely degraded by short channel effects in the sub-65nm regime. In such a scenario, the Silicon-on-Insulator (SOI) technology looks set to become the next driver of CMOS scaling. SOI has been proved capable of providing increased transistor speed, reduced power consumption and enhanced device scalability as demanded by the 65nm and beyond technology generations. The problems facing SOI include fabrication of thin silicon and buried oxide (BOX) films and high manufacturing cost. This thesis focuses on a novel approach to building a SOI substrate which uses an epitaxial oxide as template to grow silicon on top. The novel "Floating Epitaxy SOI" aims to guarantee thin silicon films and low manufacturing cost. This research work involves modeling ultra-thin body fully depleted SOI devices from 60nm gate length down to 10nm gate length. The device uses metalD igh-k gatestack and strained silicon as attractive features for better device performance. The goal of this work is to re-engineer the device structure and alter device design parameters at every gate length such that device performance meets the semiconductor roadmap projections in terms of off-state leakage current and ratio of drive current to leakage current as specified by International Technology Roadmap for Semiconductors. (ITRS) A challenge to better device performance is the high permittivity of candidate epitaxial oxides. It is well established that high permittivity buried oxide layer adds additional short channel effects. This makes device design and control of short channel effects more difficult. The major findings of this thesis are that ultra-thin body SOI devices based on "Floating Epitaxy SOI" meet ITRS projections down to 10nm gate length. Moreover, for sub-15nm devices that require ult.
Silicon-on-insulator Technology and Devices XI
Author: Electrochemical Society. MeetingPublisher: The Electrochemical Society
ISBN: 9781566773751
Category : Science
Languages : en
Pages : 538
Book Description