Mixed Signal Circuit Verification Using Symbolic Model Checking Techniques PDF Download

Author: Alexander Jesser
Publisher:
ISBN: 9783899638417
Category : Mixed-Signal-Schaltung - Model Checking
Languages : en
Pages : 202

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Book Description

Author: David C. Walter
Publisher:
ISBN: 9780549051701
Category : Computer software
Languages : en
Pages : 121

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Book Description
After describing the verification system in detail, experiences applying the techniques to several case studies are described and performance results are provided.

Author: Kenneth L. McMillan
Publisher: Springer Science & Business Media
ISBN: 146153190X
Category : Technology & Engineering
Languages : en
Pages : 202

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Book Description
Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. Symbolic Model Checking deals with methods of automatic verification as applied to computer hardware. The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention.

Author: Edmund Clarke
Publisher:
ISBN:
Category : Computer-aided design
Languages : en
Pages : 0

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Book Description
Abstract: "The highly-publicized division error in the Pentium has emphasized the importance of formal verification of arithmetic operations. Symbolic model checking techniques based on binary decision diagrams (BDDs) have been successful in verifying control logic. However, lack of proper representation for functions that map boolean vectors into integers has prevented this technique from being used for verifying arithmetic circuits. We have used hybrid decision diagrams to represent the integer functions that occur in the arithmetic circuit verification. For the state variables corresponding to data bits, our representation behaves like a binary moment diagram (BMD) while for the state variables corresponding to control signals, it behaves like a multi-terminal BDD (MTBDD). By using this representation, we are able to handle circuits with both control logic and wide data paths. We have extended the symbolic model checking system SMV so that it can also handle properties involving relationships among data words. In the original SMV system, atomic formulas could only contain state variables. In the extended system, we allow atomic formulas to be equations or inequalities between expressions as well. These expressions are represented as hybrid decision diagrams. The extended model checking system enables us to verify circuits for division and square root computation that are based on the SRT algorithm used by the Pentium. We are able to handle both the control logic and the data paths. The total number of state variables exceeds 600 (which is much larger than any circuit previously checked by SMV)."

Author: Edmund Clarke
Publisher:
ISBN:
Category : Computer-aided design
Languages : en
Pages : 19

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Book Description
Abstract: "The highly-publicized division error in the Pentium has emphasized the importance of formal verification of arithmetic operations. Symbolic model checking techniques based on binary decision diagrams (BDDs) have been successful in verifying control logic. However, lack of proper representation for functions that map boolean vectors into integers has prevented this technique from being used for verifying arithmetic circuits. We have used hybrid decision diagrams to represent the integer functions that occur in the arithmetic circuit verification. For the state variables corresponding to data bits, our representation behaves like a binary moment diagram (BMD) while for the state variables corresponding to control signals, it behaves like a multi-terminal BDD (MTBDD). By using this representation, we are able to handle circuits with both control logic and wide data paths. We have extended the symbolic model checking system SMV so that it can also handle properties involving relationshi

Author: Carnegie-Mellon University. Computer Science Dept
Publisher:
ISBN:
Category :
Languages : en
Pages : 50

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Author: Carnegie Mellon University. Computer Science Department
Publisher:
ISBN:
Category :
Languages : en
Pages : 0

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Book Description

Author: Mourad Fakhfakh
Publisher: Springer
ISBN: 3319198726
Category : Computers
Languages : en
Pages : 500

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Book Description
This book explains the application of recent advances in computational intelligence – algorithms, design methodologies, and synthesis techniques – to the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems. This first of two related volumes addresses the design of analog and mixed-signal (AMS) and radio-frequency (RF) circuits, with 17 chapters grouped into parts on analog and mixed-signal applications, and radio-frequency design. It will be of interest to practitioners and researchers in computer science and electronics engineering engaged with the design of electronic circuits.

Author: Mohamed Hamed Zaki Hussein
Publisher:
ISBN:
Category :
Languages : en
Pages : 382

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Book Description

Author: Leyi Yin
Publisher:
ISBN:
Category :
Languages : en
Pages :

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Book Description
As CMOS technologies continuously scale down, designing robust analog and mixed-signal (AMS) circuits becomes increasingly difficult. Consequently, there are pressing needs for AMS design checking techniques, more specifically design verification and design for testability (DfT). The purpose of verification is to ensure that the performance of an AMS design meets its specification under process, voltage and temperature (PVT) variations and different working conditions, while DfT techniques aim at embedding testability into the design, by adding auxiliary circuitries for testing purpose. This dissertation focuses on improving the robustness of AMS designs in highly scaled technologies, by developing novel formal verification and in-situ test techniques. Compared with conventional AMS verification that relies more on heuristically chosen simulations, formal verification provides a mathematically rigorous way of checking the target design property. A formal verification framework is proposed that incorporates nonlinear SMT solving techniques and simulation exploration to efficiently verify the dynamic properties of AMS designs. A powerful Bayesian inference based technique is applied to dynamically tradeoff between the costs of simulation and nonlinear SMT. The feasibility and efficacy of the proposed methodology are demonstrated on the verification of lock time specification of a charge-pump PLL. The powerful and low-cost digital processing capabilities of today's CMOS technologies are enabling many new in-situ test schemes in a mixed-signal environment. First, a novel two-level structure of GRO-PVDL is proposed for on-chip jitter testing of high-speed high-resolution applications with a gated ring oscillator (GRO) at the first level to provide a coarse measurement and a Vernier-style structure at the second level to further measure the residue from the first level with a fine resolution. With the feature of quantization noise shaping, an effective resolution of 0.8ps can be achieved using a 90nm CMOS technology. Second, the reconfigurability of recent all-digital PLL designs is exploited to provide in-situ output jitter test and diagnosis abilities under multiple parametric variations of key analog building blocks. As an extension, an in-situ test scheme is proposed to provide online testing for all-digital PLL based polar transmitters. The electronic version of this dissertation is accessible from http://hdl.handle.net/1969.1/151616