Power-Constrained Testing of VLSI Circuits PDF Download

Author: Nicola Nicolici
Publisher: Springer Science & Business Media
ISBN: 0306487314
Category : Technology & Engineering
Languages : en
Pages : 182

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Book Description
This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.

Author: Patrick Girard
Publisher: Springer Science & Business Media
ISBN: 1441909281
Category : Technology & Engineering
Languages : en
Pages : 376

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Book Description
Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.

Author: Sudarshan Bahukudumbi
Publisher: Artech House
ISBN: 1596939907
Category : Technology & Engineering
Languages : en
Pages : 198

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Book Description
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Author: David Huang
Publisher: The Electrochemical Society
ISBN: 1566777038
Category : Science
Languages : en
Pages : 1124

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Book Description
ISTC/CSTIC is an annual semiconductor technology conference covering all the aspects of semiconductor technology and manufacturing, including devices, design, lithography, integration, materials, processes, manufacturing as well as emerging semiconductor technologies and silicon material applications. ISTC/CSTIC 2009 was merged by ISTC (International Semiconductor Technology Conference) and CSTIC (China Semiconductor Technology International Conference), the two industry leading technical conferences in China, and consisted of one plenary session and nine technical symposia. This issue of ECS Transactions contains 159 papers from the conference.

Author: Nima Aghaee Ghaleshahi
Publisher: Linköping University Electronic Press
ISBN: 9176859495
Category :
Languages : en
Pages : 219

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Book Description
Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis. Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors. Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced. The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced. All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.

Author: Veena S. Chakravarthi
Publisher: Springer Science & Business Media
ISBN: 8132215249
Category : Technology & Engineering
Languages : en
Pages : 464

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Book Description
This book is a collection of papers presented by renowned researchers, keynote speakers, and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals & Systems and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17–19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers, and academicians as well as industry professionals.

Author: Raimund Ubar
Publisher: IGI Global
ISBN: 1609602145
Category : Computers
Languages : en
Pages : 580

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Book Description
"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--

Author: Hafizur Rahaman
Publisher: Springer
ISBN: 3642314945
Category : Computers
Languages : en
Pages : 427

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Book Description
This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The papers are organized in topical sections on VLSI design, design and modeling of digital circuits and systems, testing and verification, design for testability, testing memories and regular logic arrays, embedded systems: hardware/software co-design and verification, emerging technology: nanoscale computing and nanotechnology.

Author: Luciano Lavagno
Publisher: CRC Press
ISBN: 1482254638
Category : Technology & Engineering
Languages : en
Pages : 644

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Book Description
The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.

Author: Sergey Yurish
Publisher: Lulu.com
ISBN: 8469786334
Category : Technology & Engineering
Languages : en
Pages : 536

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Book Description
The 1st volume of 'Advances in Microelectronics: Reviews' Book Series contains 19 chapters written by 72 authors from academia and industry from 16 countries. With unique combination of information in each volume, the 'Advances in Microelectronics: Reviews' Book Series will be of value for scientists and engineers in industry and at universities. In order to offer a fast and easy reading of the state of the art of each topic, every chapter in this book is independent and self-contained. All chapters have the same structure: first an introduction to specific topic under study; second particular field description including sensing applications. Each of chapter is ending by well selected list of references with books, journals, conference proceedings and web sites. This book ensures that readers will stay at the cutting edge of the field and get the right and effective start point and road map for the further researches and developments.