Journal of Design Automation & Fault-tolerant Computing PDF Download

Author:
Publisher:
ISBN:
Category : Digital electronics
Languages : en
Pages : 1000

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Author: Dhiraj K. Pradhan
Publisher: Prentice Hall
ISBN: 9780130578877
Category : Computers
Languages : en
Pages : 550

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Book Description
In the ten years since the publication of the first edition of this book, the field of fault-tolerant design has broadened in appeal, particularly with its emerging application in distributed computing. This new edition specifically deals with this dynamically changing computing environment, incorporating new topics such as fault-tolerance in multiprocessor and distributed systems.

Author: Xiaowei Li
Publisher: Springer Nature
ISBN: 9811985510
Category : Computers
Languages : en
Pages : 318

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Book Description
With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.

Author: Brian Randell
Publisher: Springer Science & Business Media
ISBN: 364279789X
Category : Computers
Languages : en
Pages : 592

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Author: Barry W. Johnson
Publisher:
ISBN:
Category : Fault-tolerant computing
Languages : en
Pages : 696

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Author: Rudy Lauwereins
Publisher: Springer Science & Business Media
ISBN: 1402064888
Category : Technology & Engineering
Languages : en
Pages : 499

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In 2007 The Design, Automation and Test in Europe (DATE) conference celebrated its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry.

Author: Alwin Zulehner
Publisher: Springer
ISBN: 9783030417529
Category : Technology & Engineering
Languages : en
Pages : 22

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This book offers readers an easy introduction into quantum computing as well as into the design for corresponding devices. The authors cover several design tasks which are important for quantum computing and introduce corresponding solutions. A special feature of the book is that those tasks and solutions are explicitly discussed from a design automation perspective, i.e., utilizing clever algorithms and data structures which have been developed by the design automation community for conventional logic (i.e., for electronic devices and systems) and are now applied for this new technology. By this, relevant design tasks can be conducted in a much more efficient fashion than before – leading to improvements of several orders of magnitude (with respect to runtime and other design objectives). Describes the current state of the art for designing quantum circuits, for simulating them, and for mapping them to real hardware; Provides a first comprehensive introduction into design automation for quantum computing that tackles practically relevant tasks; Targets the quantum computing community as well as the design automation community, showing both perspectives to quantum computing, and what impressive improvements are possible when combining the knowledge of both communities.

Author: Christoforos N. Hadjicostis
Publisher: Springer Science & Business Media
ISBN: 1461508533
Category : Technology & Engineering
Languages : en
Pages : 202

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Book Description
Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems describes coding approaches for designing fault-tolerant systems, i.e., systems that exhibit structured redundancy that enables them to distinguish between correct and incorrect results or between valid and invalid states. Since redundancy is expensive and counter-intuitive to the traditional notion of system design, the book focuses on resource-efficient methodologies that avoid excessive use of redundancy by exploiting the algorithmic/dynamic structure of a particular combinational or dynamic system. The first part of Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems focuses on fault-tolerant combinational systems providing a review of von Neumann's classical work on Probabilistic Logics (including some more recent work on noisy gates) and describing the use of arithmetic coding and algorithm-based fault-tolerant schemes in algebraic settings. The second part of the book focuses on fault tolerance in dynamic systems. Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems also discusses how, in a dynamic system setting, one can relax the traditional assumption that the error-correcting mechanism is fault-free by using distributed error correcting mechanisms. The final chapter presents a methodology for fault diagnosis in discrete event systems that are described by Petri net models; coding techniques are used to quickly detect and identify failures. From the Foreword: "Hadjicostis has significantly expanded the setting to processes occurring in more general algebraic and dynamic systems... The book responds to the growing need to handle faults in complex digital chips and complex networked systems, and to consider the effects of faults at the design stage rather than afterwards." George Verghese, Massachusetts Institute of Technology Coding Approaches to Fault Tolerance in Combinational and Dynamic Systems will be of interest to both researchers and practitioners in the area of fault tolerance, systems design and control.

Author: Fevzi Belli
Publisher: Springer Science & Business Media
ISBN: 3642456286
Category : Computers
Languages : en
Pages : 401

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Book Description
Dieser Band enthält die 38 Beiträge der 3. GI/ITG/GMA-Fachtagung über "Fehlertolerierende Rechensysteme". Unter den 10 aus dem Ausland eingegangenen Beiträgen sind 4 eingeladene Vorträge. Insgesamt dokumentiert dieser Tagungsband die Entwicklung der Konzeption und Implementierung fehlertoleranter Systeme in den letzten drei Jahren vor allem in Europa. Sämtliche Beiträge sind neue Forschungs- oder Entwicklungsergebnisse, die vom Programmausschuß der Tagung aus 70 eingereichten Beiträgen ausgewählt wurden.

Author: Krishnendu Chakrabarty
Publisher: Springer Science & Business Media
ISBN: 1475765274
Category : Technology & Engineering
Languages : en
Pages : 202

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Book Description
System-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is a valuable reference for researchers and students interested in various aspects of SOC testing.