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Author: Brian J. Malley Publisher: ISBN: 9781369339291 Category : Error-correcting codes (Information theory) Languages : en Pages : 72
Book Description
Abstract: Soft errors caused by radiation are a common problem in spaceflight due to the intense radiation environment of space. Single Error Correction (SEC) Error Correcting Codes (ECCs) are a traditional approach to solve this problem, but with the increasing density of IC architectures, multiple-bit errors are becoming more common. Double Error Correction (DEC) ECCs are costly, but codes between DEC and SEC, which take advantage of the spatial locality of bit errors and correct only adjacent double-bit errors, have been found by others. In this thesis, one of those codes is implemented and evaluated on a Spartan-6 FPGA. The results of several error trials are presented herein, along with implementation details, including the source code. Tables of the trial results and the specific FPGA resources used are also presented. The implementation is found to have a non-negligible area cost, but low latency cost. Another implementation of this same ECC with potentially low area but high latency is also described. When errors well beyond the ECC's capability, such as multiple single-bit errors, or four-bit errors, are injected, around 30% of the time the code erroneously claims to have fixed an error. In these same circumstances, however, the ECC implementation hardly ever (0.2%) claims that no error has occurred. This suggests that a simple extension to a more conservative ECC which flushes data on any error could be used in situations with error rates that surpass the ECC's capability to maintain data integrity.
Author: Brian J. Malley Publisher: ISBN: 9781369339291 Category : Error-correcting codes (Information theory) Languages : en Pages : 72
Book Description
Abstract: Soft errors caused by radiation are a common problem in spaceflight due to the intense radiation environment of space. Single Error Correction (SEC) Error Correcting Codes (ECCs) are a traditional approach to solve this problem, but with the increasing density of IC architectures, multiple-bit errors are becoming more common. Double Error Correction (DEC) ECCs are costly, but codes between DEC and SEC, which take advantage of the spatial locality of bit errors and correct only adjacent double-bit errors, have been found by others. In this thesis, one of those codes is implemented and evaluated on a Spartan-6 FPGA. The results of several error trials are presented herein, along with implementation details, including the source code. Tables of the trial results and the specific FPGA resources used are also presented. The implementation is found to have a non-negligible area cost, but low latency cost. Another implementation of this same ECC with potentially low area but high latency is also described. When errors well beyond the ECC's capability, such as multiple single-bit errors, or four-bit errors, are injected, around 30% of the time the code erroneously claims to have fixed an error. In these same circumstances, however, the ECC implementation hardly ever (0.2%) claims that no error has occurred. This suggests that a simple extension to a more conservative ECC which flushes data on any error could be used in situations with error rates that surpass the ECC's capability to maintain data integrity.
Author: Cyrille Chavet Publisher: Springer ISBN: 3319105698 Category : Technology & Engineering Languages : en Pages : 197
Book Description
This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.
Author: R. K. Nagaria Publisher: Springer Nature ISBN: 9819909732 Category : Technology & Engineering Languages : en Pages : 867
Book Description
This book covers a variety of topics in Electronics and Communication Engineering, especially in the area of microelectronics and VLSI design, communication systems and networks, and signal and image processing. The content is based on papers presented at the 5th International Conference on VLSI, Communication and Signal Processing (VCAS 2022). The book also discusses the emerging applications of novel tools and techniques in image, video, and multimedia signal processing. This book is useful to students, researchers, and professionals working in the electronics and communication domain.
Author: Sumit Kundu Publisher: Springer Nature ISBN: 9811508291 Category : Technology & Engineering Languages : en Pages : 720
Book Description
This book gathers high-quality papers presented at the 2nd International Conference on Communication, Devices & Computing (ICCDC 2019), held at Haldia Institute of Technology from March 14–15, 2019. The papers are divided into three main areas: communication technologies, electronics circuits & devices and computing. Written by students and researchers from around the world, they accurately reflect the global status quo.
Author: Anusha Nandagopal Publisher: ISBN: Category : Languages : en Pages : 252
Book Description
Error-control coding is a special subject with its own history and arithmetic systems. The theory and usage of error-control codes relate to the protection of digital information against errors that occur during data transmission and storage. Error correction coding attaches redundancy to the data at the system's error correction encoder and uses that redundancy to correct erroneous data at the error correction decoder.This thesis focuses on error correcting codes and the hardware implementation of two error-control codes - Reed-Solomon (RS) codes and Viterbi's algorithm. Prior to emphasizing on these two codes, a brief description of various other types of error correcting schemes is presented. A simple (15, 9) RS code and a (4, 1, 2) convolutional code are taken to elaborate the encoding and decoding processes for these error correcting codes. The primary objective of this thesis is to provide a simple and efficient hardware for reliably transmitting and receiving message bits across a communication channel.
Author: Radek Silhavy Publisher: Springer Nature ISBN: 3030519740 Category : Technology & Engineering Languages : en Pages : 650
Book Description
This book gathers the refereed proceedings of the Applied Informatics and Cybernetics in Intelligent Systems Section of the 9th Computer Science On-line Conference 2020 (CSOC 2020), held on-line in April 2020. Modern cybernetics and computer engineering in connection with intelligent systems are an essential aspect of ongoing research. This book addresses these topics, together with automation and control theory, cybernetic applications, and the latest research trends.
Author: Roger Woods Publisher: John Wiley & Sons ISBN: 1119077958 Category : Technology & Engineering Languages : en Pages : 356
Book Description
An important working resource for engineers and researchers involved in the design, development, and implementation of signal processing systems The last decade has seen a rapid expansion of the use of field programmable gate arrays (FPGAs) for a wide range of applications beyond traditional digital signal processing (DSP) systems. Written by a team of experts working at the leading edge of FPGA research and development, this second edition of FPGA-based Implementation of Signal Processing Systems has been extensively updated and revised to reflect the latest iterations of FPGA theory, applications, and technology. Written from a system-level perspective, it features expert discussions of contemporary methods and tools used in the design, optimization and implementation of DSP systems using programmable FPGA hardware. And it provides a wealth of practical insights—along with illustrative case studies and timely real-world examples—of critical concern to engineers working in the design and development of DSP systems for radio, telecommunications, audio-visual, and security applications, as well as bioinformatics, Big Data applications, and more. Inside you will find up-to-date coverage of: FPGA solutions for Big Data Applications, especially as they apply to huge data sets The use of ARM processors in FPGAs and the transfer of FPGAs towards heterogeneous computing platforms The evolution of High Level Synthesis tools—including new sections on Xilinx's HLS Vivado tool flow and Altera's OpenCL approach Developments in Graphical Processing Units (GPUs), which are rapidly replacing more traditional DSP systems FPGA-based Implementation of Signal Processing Systems, 2nd Edition is an indispensable guide for engineers and researchers involved in the design and development of both traditional and cutting-edge data and signal processing systems. Senior-level electrical and computer engineering graduates studying signal processing or digital signal processing also will find this volume of great interest.
Author: Amos R. Omondi Publisher: Springer Science & Business Media ISBN: 0387284877 Category : Technology & Engineering Languages : en Pages : 365
Book Description
During the 1980s and early 1990s there was signi?cant work in the design and implementation of hardware neurocomputers. Nevertheless, most of these efforts may be judged to have been unsuccessful: at no time have have ha- ware neurocomputers been in wide use. This lack of success may be largely attributed to the fact that earlier work was almost entirely aimed at developing custom neurocomputers, based on ASIC technology, but for such niche - eas this technology was never suf?ciently developed or competitive enough to justify large-scale adoption. On the other hand, gate-arrays of the period m- tioned were never large enough nor fast enough for serious arti?cial-neur- network (ANN) applications. But technology has now improved: the capacity and performance of current FPGAs are such that they present a much more realistic alternative. Consequently neurocomputers based on FPGAs are now a much more practical proposition than they have been in the past. This book summarizes some work towards this goal and consists of 12 papers that were selected, after review, from a number of submissions. The book is nominally divided into three parts: Chapters 1 through 4 deal with foundational issues; Chapters 5 through 11 deal with a variety of implementations; and Chapter 12 looks at the lessons learned from a large-scale project and also reconsiders design issues in light of current and future technology.
Author: S. Rajaram Publisher: Springer ISBN: 9811359504 Category : Computers Languages : en Pages : 728
Book Description
This book constitutes the refereed proceedings of the 22st International Symposium on VLSI Design and Test, VDAT 2018, held in Madurai, India, in June 2018. The 39 full papers and 11 short papers presented together with 8 poster papers were carefully reviewed and selected from 231 submissions. The papers are organized in topical sections named: digital design; analog and mixed signal design; hardware security; micro bio-fluidics; VLSI testing; analog circuits and devices; network-on-chip; memory; quantum computing and NoC; sensors and interfaces.
Author: Brian J. Malley
Author: Brian J. Malley
Author: Cyrille Chavet
Author: Rayfield Kenneth Wert
Author: R. K. Nagaria
Author: Sumit Kundu
Author: Anusha Nandagopal
Author: Radek Silhavy
Author: Roger Woods
Author: Amos R. Omondi
Author: S. Rajaram