High Mobility Strained Si/SiGe Heterostructure MOSFETs PDF Download

Author: Christopher W. Leitz
Publisher:
ISBN:
Category : Metal oxide semiconductor field-effect transistors
Languages : en
Pages : 178

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Book Description
(Cont.) Record mobility strained Si p-MOSFETs have been fabricated on relaxed 40% Ge virtual substrates. Hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with mobility enhancements over twice that of co-processed bulk Si devices. In contrast, hole mobility in strained Si p-MOSFETs displays no strong dependence on strained layer thickness. These results indicate that strain is the primary variable in determining hole mobility in strained Si p-MOSFETs and that symmetric electron and hole mobility enhancements in strained Si MOSFETs can be obtained for virtual substrate compositions beyond 35% Ge. The effect of alloy scattering on carrier mobility in tensile strained SiGe surface channel MOSFETs is measured directly for the first time. Electron mobility is degraded much more severely than hole mobility in these heterostructures, in agreement with theoretical predictions. Dual channel heterostructures, which consist of the combination of buried compressively strained SiilyGey buried channels and tensile strained Si surface channels, grown on relaxed SilxGex virtual substrates, are explored in detail for the first time. Hole mobilities exceeding 700 cm2/V-s have been achieved by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. This layer sequence exhibits nearly symmetric electron and hole mobilities, both enhanced relative to bulk Si ...

Author: C.K Maiti
Publisher: CRC Press
ISBN: 1420012347
Category : Science
Languages : en
Pages : 438

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Book Description
A combination of the materials science, manufacturing processes, and pioneering research and developments of SiGe and strained-Si have offered an unprecedented high level of performance enhancement at low manufacturing costs. Encompassing all of these areas, Strained-Si Heterostructure Field Effect Devices addresses the research needs associated wi

Author: Puneet Goyal
Publisher:
ISBN:
Category : Compound semiconductors
Languages : en
Pages : 212

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Book Description
"With a unified physics-based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process-induced and global-induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon-germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature. A dual channel heterostructure consisting of strained Si/Si1-xGex on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics-based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n-channel drive currents of 0.43 and 0.98 mA/Gm, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device"--Abstract.

Author: Ingvar Åberg
Publisher:
ISBN:
Category :
Languages : en
Pages : 183

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(Cont.) Comparisons between SSDOI of two strain levels indicate benefits of strain engineering down to 3 nm thickness. The hole mobility in HOI is improved compared to that in SSDOI, due to the high hole mobility in the Si1-zGez channel. The mobility enhancement is similar at low and high hole densities even at moderate strain levels. The hole mobility in HOI with SiGe channel thickness below 10 nm is observed to follow a similar dependence on channel thickness as hole mobility in SSDOI. Simulations of electrostatics in HOI and SSDOI with ultra-thin channel thicknesses indicate similarities in the confinement of the inversion charge in ultra-thin body HOI and SSDOI. This suggests that the similar reduction of hole mobility in HOI and SSDOI with 4-10 nm-thick channels is associated with an increase in phonon scattering from the reduced effective channel thickness.

Author: Mark Albert Armstrong
Publisher:
ISBN:
Category : Germanium compounds
Languages : en
Pages : 312

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Book Description
Bulk silicon is currently the substrate material of choice for the manufacture of high performance digital circuits due to its highly-developed processing technology and the relatively low cost for high-quality substrates. Silicon-based MOSFETs have reached remarkable levels of performance through device scaling. However, with each technology generation, it is becoming harder and harder to improve device performance at the same pace through traditional scaling methods alone. Short-channel effects such as velocity saturation and drain-induced barrier lowering have placed an fundamental limit on the ultimate performance of bulk Si MOSFETS. One way to raise this limit is to increase the carrier mobilities in the channel. This can be done using high-mobility Si and SiGe strained-layers. Unlike III-V-based high-mobility materials, Si/SiGe strained-layers have the advantage of being largely compatible with mainstream Si processing, which is important from a financial feasibility standpoint. This thesis examines several issues related to Si/SiGe strained-layer devices and their integration into mainstream CMOS. The first part of this work strives to predict the performance leverage of high-mobility Si/ SiGe over bulk Si devices and circuits in a realistic manner. Two-dimensional hydrodynamic simulations are used to predict static device characteristics including effects of series resistance, velocity saturation and velocity overshoot. The simulations show enhanced current drive over bulk Si devices at 0.2 [mu]m effective channel length and highlight the importance of velocity overshoot in high-mobility submicron devices. The circuit performance of Si/SiGe devices is determined from transient simulations of CMOS ring oscillators including the effects of parasitic capacitance and drain-to-source voltage at the onset of saturation Vds.sat. The simulations show a 4 to 6-fold reduction in power-delay product as compared to bulk CMOS oscillators operated at 2.5 V with the same design rules. The remainder of the thesis focuses on the fabrication and characterization of strained-Si NMOS devices. The vehicle for this work is a novel short-flow, single-mask MOSFET which can be fabbed in as little as a week. This device is superior to simple Hall mobility structures which suffer from leakage through the substrate, an inability to control the. carrier concentration and the uncertainty associated with the Hall scattering factor. I investigate a novel buried-channel strained-Si NMOS structure incorporating an n-type donor layer beneath the strained-Si channel to encourage occupation of the buried channel and increase the overall mobility. Peak mobility in a structure without a donor layer reproduces the best results in the literature for buried-channel strained-Si NMOS devices. For structures with donor layers, Coulomb scattering from charges in the donor layer eradicates any benefit from increased buried-channel occupation. I also investigate the effect of well implants on the mobility of surface . channel strained-Si NMOS devices. Similar to the universal mobility curve in bulk Si, mobility at low perpendicular electric field degrades with increasing implant dose while high field mobility is unaffected. The mobility is largely unaffected by a neutral implant species at the same dose. This leads to the conclusion that the material quality of the strained-layer is not affected by the implant, and that the mobility degradation is due solely to increased ionized impurity scattering.

Author: C. K. Maiti
Publisher: IET
ISBN: 9780852967782
Category : Technology & Engineering
Languages : en
Pages : 520

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Book Description
This book comprehensively covers the areas of materials growth, characterisation and descriptions for the new devices in siliconheterostructure material systems. In recent years, the development of powerful epitaxial growth techniques such as molecular beam epitaxy (MBE), ultra-high vacuum chemical vapour deposition (UHVCVD) and other low temperature epitaxy techniques has given rise to a new area of research of bandgap engineering in silicon-based materials. This has paved the way not only for heterojunction bipolar and field effect transistors, but also for other fascinating novel quantum devices. This book provides an excellent introduction and valuable references for postgraduate students and research scientists.

Author: David Louis Harame
Publisher: The Electrochemical Society
ISBN: 1566775078
Category : Electronic apparatus and appliances
Languages : en
Pages : 1280

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Book Description
The second International SiGe & Ge: Materials, Processing, and Devices Symposium was part of the 2006 ECS conference held in Cancun, Mexico from October 29-Nov 3, 2006. This meeting provided a forum for reviewing and discussing all materials and device related aspects of SiGe & Ge. The hardcover edition includes a bonus CD-ROM containing the PDF of the entire issue.

Author: John D. Cressler
Publisher: CRC Press
ISBN: 1420026585
Category : Technology & Engineering
Languages : en
Pages : 1248

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Book Description
An extraordinary combination of material science, manufacturing processes, and innovative thinking spurred the development of SiGe heterojunction devices that offer a wide array of functions, unprecedented levels of performance, and low manufacturing costs. While there are many books on specific aspects of Si heterostructures, the Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy is the first book to bring all aspects together in a single source. Featuring broad, comprehensive, and in-depth discussion, this handbook distills the current state of the field in areas ranging from materials to fabrication, devices, CAD, circuits, and applications. The editor includes "snapshots" of the industrial state-of-the-art for devices and circuits, presenting a novel perspective for comparing the present status with future directions in the field. With each chapter contributed by expert authors from leading industrial and research institutions worldwide, the book is unequalled not only in breadth of scope, but also in depth of coverage, timeliness of results, and authority of references. It also includes a foreword by Dr. Bernard S. Meyerson, a pioneer in SiGe technology. Containing nearly 1000 figures along with valuable appendices, the Silicon Heterostructure Handbook authoritatively surveys materials, fabrication, device physics, transistor optimization, optoelectronics components, measurement, compact modeling, circuit design, and device simulation.

Author: C.K. Maiti
Publisher: CRC Press
ISBN: 1466503475
Category : Technology & Engineering
Languages : en
Pages : 320

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Book Description
Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale. This book focuses on recent developments in strain-engineered MOSFETS implemented in high-mobility substrates such as, Ge, SiGe, strained-Si, ultrathin germanium-on-insulator platforms, combined with high-k insulators and metal-gate. It covers the materials aspects, principles, and design of advanced devices, fabrication, and applications. It also presents a full technology computer aided design (TCAD) methodology for strain-engineering in Si-CMOS technology involving data flow from process simulation to process variability simulation via device simulation and generation of SPICE process compact models for manufacturing for yield optimization. Microelectronics fabrication is facing serious challenges due to the introduction of new materials in manufacturing and fundamental limitations of nanoscale devices that result in increasing unpredictability in the characteristics of the devices. The down scaling of CMOS technologies has brought about the increased variability of key parameters affecting the performance of integrated circuits. This book provides a single text that combines coverage of the strain-engineered MOSFETS and their modeling using TCAD, making it a tool for process technology development and the design of strain-engineered MOSFETs.

Author: Hasan Munir Nayfeh
Publisher:
ISBN:
Category :
Languages : en
Pages : 179

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Book Description
This thesis presents work aimed at investigating the possible benefit of strained-Si/SiGe heterostructure MOSFETs designed for nanoscale (sub-50-nm) gate lengths with the aid of device fabrication and electrical measurements combined with computer simulation. MOSFET devices fabricated on bulk-Si material are scaled in order to achieve gains in performance and integration. However, as device dimensions continue to scale, physical constraints are being reached that may limit continued scaling and/or the gains in performance from scaling. In order to continue the benefits of scaling, a possible solution is to change to a strained-Si/SiGe material system where enhanced electron mobility of 1.7-2X has been demonstrated for long-channel n-type devices. The electron mobility enhancement observed for long channel length devices may not be the same for devices with nanoscale gate length. In particular, increased channel doping, which is required to control short-channel effects can result in degraded transport characteristics. In this work, the impact of high channel doping on mobility enhancements in strained-Si n-MOSFETs is investigated experimentally. Increased channel doping will increase Coulomb scattering interactions increasing its influence on the overall mobility. Electron transport models were calibrated using experimental data for both strained and un-strained Si devices for various channel doping concentrations. The transport models were then used to investigate, by computer simulation, the performance enhancement of nanoscale strained Si devices for equivalent off-current.