High Efficiency Wideband Low-power Delta-sigma Modulators PDF Download

Author: Sang Hyeon Lee
Publisher:
ISBN:
Category : Analog-to-digital converters
Languages : en
Pages : 91

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Book Description
Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and wireless communication systems. Therefore, power efficient wideband low power delta-sigma data converters that bridges analog and digital have become mandatory for popular mobile applications today. In this dissertation, two architectural innovations and a development and realization of a state-of-the-art delta-sigma analog to digital converter with effective design techniques in both architectural and circuit levels are presented. The first one is timing-relaxed double noise coupling which effectively provides 2nd order noise shaping in the noise transfer function and overcomes stringent timing requirement for quantization and DEM. The second one presented is a noise shaping SAR quantizer, which provides one order of noise shaping in the noise transfer function. It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion delta-sigma modulator which is suitable for adopting SAR quantizer. Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for WLAN applications is presented. It uses a noise folding free double sampling technique and an improved low-distortion architecture with an embedded-adder integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18[micro]m CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27 pJ/conv-step. The measurement results indicate that the proposed design ideas are effective and useful for wideband, low power delta-sigma analog-to-digital converters with low oversampling ratio.

Author: Friedel Gerfers
Publisher: Springer Science & Business Media
ISBN: 3540284737
Category : Technology & Engineering
Languages : en
Pages : 257

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Book Description
Sigma-delta A/D converters are a key building block in wireless and multimedia applications. This comprehensive book deals with all relevant aspects arising during the analysis, design and simulation of the now widespread continuous-time implementations of sigma-delta modulators. The results of several years of research by the authors in the field of CT sigma-delta modulators are covered, including the analysis and modeling of different CT modulator architectures, CT/DT loop filter synthesis, a detailed error analysis of all components, and possible compensation/correction schemes for the non-ideal behavior in CT sigma-delta modulators. Guidance for obtaining low-power consumption and several practical implementations are also presented. It is shown that all the proposed new theories, architectures and possible correction techniques have been confirmed by measurements on discrete or integrated circuits. Quantitative results are also provided, thus enabling prediction of the resulting accuracy.

Author: Shahriar Rabii
Publisher: Springer Science & Business Media
ISBN: 1461551056
Category : Technology & Engineering
Languages : en
Pages : 198

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Book Description
Oversampling techniques based on sigma-delta modulation are widely used to implement the analog/digital interfaces in CMOS VLSI technologies. This approach is relatively insensitive to imperfections in the manufacturing process and offers numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in the low-voltage environment that is increasingly demanded by advanced VLSI technologies and by portable electronic systems. In The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, an analysis of power dissipation in sigma-delta modulators is presented, and a low-voltage implementation of a digital-audio performance A/D converter based on the results of this analysis is described. Although significant power savings can typically be achieved in digital circuits by reducing the power supply voltage, the power dissipation in analog circuits actually tends to increase with decreasing supply voltages. Oversampling architectures are a potentially power-efficient means of implementing high-resolution A/D converters because they reduce the number and complexity of the analog circuits in comparison with Nyquist-rate converters. In fact, it is shown that the power dissipation of a sigma-delta modulator can approach that of a single integrator with the resolution and bandwidth required for a given application. In this research the influence of various parameters on the power dissipation of the modulator has been evaluated and strategies for the design of a power-efficient implementation have been identified. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators begins with an overview of A/D conversion, emphasizing sigma-delta modulators. It includes a detailed analysis of noise in sigma-delta modulators, analyzes power dissipation in integrator circuits, and addresses practical issues in the circuit design and testing of a high-resolution modulator. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators will be of interest to practicing engineers and researchers in the areas of mixed-signal and analog integrated circuit design.

Author: Xuefeng Chen
Publisher:
ISBN: 9781109914726
Category : Analog-to-digital converters
Languages : en
Pages : 125

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Book Description
In this thesis, a wideband low-power CT DeltaSigma modulator for next generation wireless applications is proposed to achieve 10-bit dynamic range within a 25 MHz signal bandwidth. On the system level, a low-power, mainly feed-forward architecture is used to realize the loop filter. Feed-in branches are added and optimized to eliminate the out-of-band peaking in the signal transfer function. On the circuit level, two-stage operational amplifiers with class-AB output stages are used to implement low-power active RC integrators. Capacitor tuning is used to compensate the variation of RC time constants. In addition, a fast current adder, an 11-level internal flash ADC and three current feedback DACs are also integrated on the chip which was manufactured in TSMC 0.18 mum CMOS technology. The test results show that the modulator draws less than 10 mA from the 1.8 V supply voltage.

Author: James A. Cherry
Publisher: Springer Science & Business Media
ISBN: 0306470527
Category : Technology & Engineering
Languages : en
Pages : 272

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Book Description
Among analog-to-digital converters, the delta-sigma modulator has cornered the market on high to very high resolution converters at moderate speeds, with typical applications such as digital audio and instrumentation. Interest has recently increased in delta-sigma circuits built with a continuous-time loop filter rather than the more common switched-capacitor approach. Continuous-time delta-sigma modulators offer less noisy virtual ground nodes at the input, inherent protection against signal aliasing, and the potential to use a physical rather than an electrical integrator in the first stage for novel applications like accelerometers and magnetic flux sensors. More significantly, they relax settling time restrictions so that modulator clock rates can be raised. This opens the possibility of wideband (1 MHz or more) converters, possibly for use in radio applications at an intermediate frequency so that one or more stages of mixing might be done in the digital domain. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits covers all aspects of continuous-time delta-sigma modulator design, with particular emphasis on design for high clock speeds. The authors explain the ideal design of such modulators in terms of the well-understood discrete-time modulator design problem and provide design examples in Matlab. They also cover commonly-encountered non-idealities in continuous-time modulators and how they degrade performance, plus a wealth of material on the main problems (feedback path delays, clock jitter, and quantizer metastability) in very high-speed designs and how to avoid them. They also give a concrete design procedure for a real high-speed circuit which illustrates the tradeoffs in the selection of key parameters. Detailed circuit diagrams, simulation results and test results for an integrated continuous-time 4 GHz band-pass modulator for A/D conversion of 1 GHz analog signals are also presented. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits concludes with some promising modulator architectures and a list of the challenges that remain in this exciting field.

Author: Fernando Medeiro
Publisher: Springer Science & Business Media
ISBN: 1475730039
Category : Technology & Engineering
Languages : en
Pages : 303

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Book Description
The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.

Author: Yan Wang
Publisher:
ISBN:
Category : Analog-to-digital converters
Languages : en
Pages : 338

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Book Description
Delta-Sigma analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a [Delta-Sigma] modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT [Delta-Sigma] ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT [Delta-Sigma] ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT [Delta-Sigma] ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT [Delta-Sigma] ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT [Delta-Sigma] ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT [Delta-Sigma] ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT [Delta-Sigma] ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected.

Author: David Fouto
Publisher: Springer
ISBN: 3319570331
Category : Technology & Engineering
Languages : en
Pages : 85

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Book Description
This book presents the study, design, modulation, optimization and implementation of low power, passive DT-ΣΔMs for use in audio applications. The high gain and bandwidth amplifier normally used for integration in ΣΔ modulation, is replaced by passive, switched-capacitor branches working under the Ultra Incomplete Settling (UIS) condition, leading to a reduction of the consumed power. The authors describe a design process that uses high level models and an optimization process based in genetic algorithms to achieve the desired performance.

Author: Steven R. Norsworthy
Publisher: Wiley-IEEE Press
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 522

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Book Description
This comprehensive guide offers a detailed treatment of the analysis, design, simulation and testing of the full range of today's leading delta-sigma data converters. Written by professionals experienced in all practical aspects of delta-sigma modulator design, Delta-Sigma Data Converters provides comprehensive coverage of low and high-order single-bit, bandpass, continuous-time, multi-stage modulators as well as advanced topics, including idle-channel tones, stability, decimation and interpolation filter design, and simulation.

Author: Mohammad Ranjbar
Publisher:
ISBN:
Category : Analog-to-digital converters
Languages : en
Pages : 206

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Book Description
This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.