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Author: Bruce Wile Publisher: Morgan Kaufmann ISBN: 0127518037 Category : Computers Languages : en Pages : 703
Book Description
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.
Author: Bruce Wile Publisher: Morgan Kaufmann ISBN: 0127518037 Category : Computers Languages : en Pages : 703
Book Description
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.
Author: Mukund Sivaraman Publisher: Springer Science & Business Media ISBN: 1441985786 Category : Technology & Engineering Languages : en Pages : 164
Book Description
Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
Author: Lingkan Gong Publisher: Springer ISBN: 3319068385 Category : Technology & Engineering Languages : en Pages : 232
Book Description
This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended Re Channel is a System C library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification.
Author: Bob Zeidman Publisher: CRC Press ISBN: 0080494455 Category : Computers Languages : en Pages : 224
Book Description
* Choose the right programmable logic devices and development tools * Understand the design, verification, and testing issues * Plan schedules and allocate resources efficiently Choose the right programmable logic devices with this guide to the technolog
Author: Richard J. Boulton Publisher: Springer ISBN: 3540447555 Category : Computers Languages : en Pages : 405
Book Description
This volume constitutes the proceedings of the 14th International Conference on Theorem Proving in Higher Order Logics (TPHOLs 2001) held 3–6 September 2001 in Edinburgh, Scotland. TPHOLs covers all aspects of theorem proving in higher order logics, as well as related topics in theorem proving and veri?cation. TPHOLs 2001 was collocated with the 11th Advanced Research Working Conference on Correct Hardware Design and Veri?cation Methods (CHARME 2001). This was held 4–7 September 2001 in nearby Livingston, Scotland at the Institute for System Level Integration, and a joint half-day session of talks was arranged for the 5th September in Edinburgh. An excursion to Traquair House and a banquet in the Playfair Library of Old College, University of Edinburgh were also jointly organized. The proceedings of CHARME 2001 have been p- lished as volume 2144 of Springer-Verlag’s Lecture Notes in Computer Science series, with Tiziana Margaria and Tom Melham as editors. Each of the 47 papers submitted in the full research category was refereed by at least 3 reviewers who were selected by the Program Committee. Of these submissions, 23 were accepted for presentation at the conference and publication in this volume. In keeping with tradition, TPHOLs 2001 also o?ered a venue for the presentation of work in progress, where researchers invite discussion by means of a brief preliminary talk and then discuss their work at a poster session. A supplementary proceedings containing associated papers for work in progress was published by the Division of Informatics at the University of Edinburgh.
Author: Alan Wiemann Publisher: Springer Science & Business Media ISBN: 0387717331 Category : Technology & Engineering Languages : en Pages : 289
Book Description
The Integrated Circuit (IC) industry has gone without a standardized verification approach for decades. This book defines a uniform, standardizable methodology for verifying the logical behavior of an integrated circuit, whether an I/O controller, a microprocessor, or a complete digital system. This book will help Engineers and managers responsible for IC development to bring a single, standards-based methodology to their R & D efforts, cutting costs and improving results.
Author: Tiziana Margaria Publisher: Springer Science & Business Media ISBN: 3642165575 Category : Computers Languages : en Pages : 726
Book Description
The two volume set LNCS 6415 and LNCS 6416 constitutes the refereed proceedings of the 4th International Symposium on Leveraging Applications of Formal Methods, ISoLA 2010, held in Heraklion, Crete, Greece, in October 2010. The 100 revised full papers presented were carefully revised and selected from numerous submissions and discuss issues related to the adoption and use of rigorous tools and methods for the specification, analysis, verification, certification, construction, test, and maintenance of systems. The 46 papers of the first volume are organized in topical sections on new challenges in the development of critical embedded systems, formal languages and methods for designing and verifying complex embedded systems, worst-case traversal time (WCTT), tools in scientific workflow composition, emerging services and technologies for a converging telecommunications / Web world in smart environments of the internet of things, Web science, model transformation and analysis for industrial scale validation, and learning techniques for software verification and validation. The second volume presents 54 papers addressing the following topics: EternalS: mission and roadmap, formal methods in model-driven development for service-oriented and cloud computing, quantitative verification in practice, CONNECT: status and plans, certification of software-driven medical devices, modeling and formalizing industrial software for verification, validation and certification, and resource and timing analysis.
Author: Angela Krstic Publisher: Springer Science & Business Media ISBN: 1461555973 Category : Technology & Engineering Languages : en Pages : 201
Book Description
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Author: Robert B. Jones Publisher: Springer Science & Business Media ISBN: 1461511011 Category : Technology & Engineering Languages : en Pages : 159
Book Description
This volume contains two distinct, but related, approaches to the verification problem, both based on symbolic simulation. It describes new ideas that enable the use of formal methods, specifically symbolic simulation, in validating commercial hardware designs of remarkable complexity.
Author: Bruce Wile
Author: Bruce Wile
Author: Mukund Sivaraman
Author: Lingkan Gong
Author: Bob Zeidman
Author: Richard J. Boulton
Author: Alan Wiemann
Author: Tiziana Margaria
Author: Angela Krstic
Author: 
Author: Robert B. Jones