Author: Robert B. SieffertPublisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
Fault Diagnosis in Combinational Logic Networks
Fault Diagnosis of Multiple Output Combinational Logic Networks
Author: Heramb SinghFault Detection Tests for Combinational Logic Networks
Author: Daniel Charles ScavezzePublisher:
ISBN:
Category :
Languages : en
Pages : 162
Book Description
Multiple Fault Diagnosis in Combinational Networks
Author: Charles Wei-Yuan ChaPublisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
A Study of Fault Diagnosis of Sequential Logic Networks
Author: B. D. CarrollPublisher:
ISBN:
Category :
Languages : en
Pages : 25
Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
Sequential Decision Trees for Fault Diagnosis in Combinational Logic Networks
Author: Doctor Israel KorenOn Fault Diagnosis
Author: Louis Gwo-Jiun ChuPublisher:
ISBN:
Category : Electric network analysis
Languages : en
Pages : 334
Book Description
Fault Analysis of Combinational Logic Networks
Author: Lung-Hsiung ChangPublisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 248
Book Description
Fault Detection Methods in Combinational Digital Logic Networks
Author: Harold M. LevyPublisher:
ISBN:
Category :
Languages : en
Pages : 133
Book Description
The ability to test a digital network as simply as possible has become quite important recently due to advances in integrated circuit technology and the consequent increases in the complexity of the networks being produced. The paper presents several existing methods of 'fault detection test generation'. A new approach to the problem of finding a minimal test set is then presented. The test set is obtained by solving a set of equations which are obtained directly from the network. It is shown that the solutions to these equations constitute a complete test set both for a nonreconvergent fanout network and for a reconvergent fanout network. A general solution procedure is presented which will generate a minimal test set for any network. An algorithm for generating a minimal test set for a nonreconvergent fanout network is also presented. (Author).
Fault Detection in Combinational Networks
Author: Alexander RahmPublisher:
ISBN:
Category : Computer system failures
Languages : en
Pages : 92
Book Description
"This paper presents an algorithm for locating a failure in combinational logic networks, which is a problem of importance in the maintenance of computer systems. The procedure is based on the "path sensitizing" idea for fault detection. The networks considered are non-redundant, consisting of AND, OR, and NOT elements. The class of faults investigated is that which causes a connection to appear to be logically suck-at-one or stuck-at-zero, and only single failures are treated. It is shown that the failure is generally located to a specific "fault group"--Abstract, leaf 2.