Author: Daniel Charles ScavezzePublisher:
ISBN:
Category :
Languages : en
Pages : 162
Book Description
Fault Detection Tests for Combinational Logic Networks
Author: Daniel Charles ScavezzePublisher:
ISBN:
Category :
Languages : en
Pages : 162
Book Description
Automated Multiple Fault Test Generation for Combinational Networks
Author: Robert A. HendrixPublisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.
Efficient Generation of Minimum Fault Test Schedules for Combinational Logic Networks
Author: William Alfred HornfeckPublisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 190
Book Description
A number of fault detection procedures for combinational logic networks are discussed and efficient algorithms are developed for the automatic generation of network test inputs. Each of the algorithms is specialized in the sense that each is designed to generate tests for a specific class of logic networks. The analysis and development of the algorithms is based on the assumption of a single error in the form of a struck-at-one or struck-at-zero fault. Algorithms are also included which can be used for no-fan-out networks, sum-of-products and product-of-sum networks, and factored realizations. Test schedules generated by the computer-aided procedures provide both a complete and minimum set of test inputs for the different types of logic networks considered. (Author).
Fault Analysis of Combinational Logic Networks
Author: Lung-Hsiung ChangPublisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 248
Book Description
Fault Detection Methods in Combinational Digital Logic Networks
Author: Harold M. LevyPublisher:
ISBN:
Category :
Languages : en
Pages : 133
Book Description
The ability to test a digital network as simply as possible has become quite important recently due to advances in integrated circuit technology and the consequent increases in the complexity of the networks being produced. The paper presents several existing methods of 'fault detection test generation'. A new approach to the problem of finding a minimal test set is then presented. The test set is obtained by solving a set of equations which are obtained directly from the network. It is shown that the solutions to these equations constitute a complete test set both for a nonreconvergent fanout network and for a reconvergent fanout network. A general solution procedure is presented which will generate a minimal test set for any network. An algorithm for generating a minimal test set for a nonreconvergent fanout network is also presented. (Author).
Multiple Faults in Combinational Logic
Author: H. G. ShahPublisher:
ISBN:
Category :
Languages : en
Pages : 72
Book Description
The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author).
Fault Detection Methods in Combinational Ditital Logic Networks
Author: Harold M. LevyPublisher:
ISBN:
Category : Combinatory logic
Languages : en
Pages : 246
Book Description
Fault Detection in Combinational Networks
Author: Alexander RahmPublisher:
ISBN:
Category : Computer system failures
Languages : en
Pages : 92
Book Description
"This paper presents an algorithm for locating a failure in combinational logic networks, which is a problem of importance in the maintenance of computer systems. The procedure is based on the "path sensitizing" idea for fault detection. The networks considered are non-redundant, consisting of AND, OR, and NOT elements. The class of faults investigated is that which causes a connection to appear to be logically suck-at-one or stuck-at-zero, and only single failures are treated. It is shown that the failure is generally located to a specific "fault group"--Abstract, leaf 2.
A Study of Fault Diagnosis of Sequential Logic Networks
Author: B. D. CarrollPublisher:
ISBN:
Category :
Languages : en
Pages : 25
Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
Author: