Author: Ramaswami DandapaniPublisher:
ISBN:
Category : Logic circuits
Languages : en
Pages : 0
Book Description
Fault Detection and the Design of Combinatorial Logic Circuits with Testability and Redundancy Criteria
Author: Ramaswami DandapaniPublisher:
ISBN:
Category : Logic circuits
Languages : en
Pages : 0
Book Description
Fault Detection and the Design of Combinational Logic Circuits with Testability and Redundancy Criteria
Author: Ramaswami DandapaniPublisher:
ISBN:
Category : Electronic circuits
Languages : en
Pages : 178
Book Description
Effects of Redundancy on Fault Detection and Diagnosis in Combinatorial Logic Circuits
Author: Howard Warren PribblePublisher:
ISBN:
Category : Computer networks
Languages : en
Pages : 258
Book Description
Effects of Redundancy on Fault Detection and Diagnosis in Combinational Logic Circuits
Author: Howard Warren PribblePublisher:
ISBN:
Category :
Languages : en
Pages : 136
Book Description
Most fault detection and diagnosis systems in use today operate under the single-fault assumption, namely that the circuits will be tested often enough so that any single fault can be detected and corrected before another fault occurs. This reasoning fails when the circuit under test contains redundancy because of the undetectable faults which redundancy implies. While an undetectable fault will not affect the logical operation of the circuit, it was demonstrated by Friedman that the presence of an undetectable fault can cause other faults (the second-generation faults) to behave differently than in the normal case or even to become undetectable. The result of this fact is that a fault which cannot be detected and therefore is not corrected, may cause tests for other faults to become invalid. To prevent this, Friedman recommended the removal of 'certain kinds of redundancy.' (Author).
Delay Testing and Design for Testability for Delay Faults in Combinatorial Logic Circuits
Author: Ankan Kumar PramanickDesign of Minimum Fault Test Schedules and Testable Realizations for Combinational Logic Circuits
Author: LeRoy Wood BearnsonPublisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 152
Book Description
Techniques for deriving the minimum length tests are developed for irredundant combinational circuits that contain single faults. The development is based on the Boolean difference function. The Boolean difference function is expanded to form two analytical expressions that can be used to calculate the tests for any stuck-at-zero and stuck-at-one fault within the circuit. A map method, that allows one to choose a minimum length test directly, is then developed from the analytical expressions. A tabular method, that is amenable to automated programming techniques, is also developed. Both the map and tabular techniques facilitate the derivation of a minimum length test, for a circuit, directly from the Boolean expression that describes it. The effect of circuit redundancy on the test length is also investigated. Bounds are established for the test length required to completely test irredundant logic circuits for single faults. The bounds can also be calculated directly from the Boolean description of the circuit in question. (Author).
Delay Testing and Design for Testability for Delay Faults in Combinational Logic Circuits
Author: Ankan Kumar PramanickPublisher:
ISBN:
Category : Logic circuits
Languages : en
Pages : 428
Book Description
Comprehensive Dissertation Index
Author: Publisher:
ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 890
Book Description
Scientific and Technical Aerospace Reports
Author: Science Abstracts
Author: Publisher:
ISBN:
Category : Electrical engineering
Languages : en
Pages : 1360
Book Description