Author: Richard James DiephuisPublisher:
ISBN:
Category :
Languages : en
Pages : 528
Book Description
Fault Analysis for Combinational Logic Networks
Author: Richard James DiephuisPublisher:
ISBN:
Category :
Languages : en
Pages : 528
Book Description
Fault Analysis of Combinational Logic Networks
Author: Lung-Hsiung ChangPublisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 248
Book Description
Fault Analysis for Computer Memory Systems and Combinational Logic Networks
Author: Alan Roger KlaytonPublisher:
ISBN:
Category : Computer storage devices
Languages : en
Pages : 346
Book Description
Multiple Fault Diagnosis in Combinational Networks
Author: Charles Wei-Yuan ChaPublisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Fault Analysis of Combinational Logic Circuits
Author: Virendra Singh NegiPublisher:
ISBN:
Category : Electric circuits
Languages : en
Pages : 100
Book Description
Fault Analysis in Logic Networks by the Boolean Differences Techniques
Author: Robert P. TruebloodA Study of Fault Diagnosis of Sequential Logic Networks
Author: B. D. CarrollPublisher:
ISBN:
Category :
Languages : en
Pages : 25
Book Description
The research conducted on this project was concerned with the problem of test pattern generation for sequential logic circuits. More specifically, an algorithm was sought for generating test patterns for detecting single stuck-at faults in synchronous sequential circuits containing clocked flip-flop memory elements. In addition to the principal problem stated above, the related problems of test pattern generation for combinational iterative logic arrays and of test pattern generation for multiple faults in combinational logic circuits were also studied. A summary of the results obtained and the conclusions reached on the above problems is given. Suggestions for follow-on studies are discussed. Reprints of all papers published on the project are included in an appendix.
A Gate Equivalent Model for Combinational Logic Network Analysis
Author: Stanford University Stanford Electronics Laboratories. Digital Systems LaboratoryPublisher:
ISBN:
Category :
Languages : en
Pages : 30
Book Description
Efficient Generation of Minimum Fault Test Schedules for Combinational Logic Networks
Author: William Alfred HornfeckPublisher:
ISBN:
Category : Electronic digital computers
Languages : en
Pages : 190
Book Description
A number of fault detection procedures for combinational logic networks are discussed and efficient algorithms are developed for the automatic generation of network test inputs. Each of the algorithms is specialized in the sense that each is designed to generate tests for a specific class of logic networks. The analysis and development of the algorithms is based on the assumption of a single error in the form of a struck-at-one or struck-at-zero fault. Algorithms are also included which can be used for no-fan-out networks, sum-of-products and product-of-sum networks, and factored realizations. Test schedules generated by the computer-aided procedures provide both a complete and minimum set of test inputs for the different types of logic networks considered. (Author).
Fault Equivalence in Combinational Logic Networks
Author: Stanford University Stanford Electronics Laboratories. Digital Systems LaboratoryPublisher:
ISBN:
Category :
Languages : en
Pages : 42
Book Description