Author: T. RamakrishnanPublisher:
ISBN:
Category :
Languages : en
Pages : 368
Book Description
Fast Fault Simulation and Compact Test Generation
Author: T. RamakrishnanFast Fault Simulation and Test Generation for PLAs in a Parallel Processing Environment
Author: International Business Machines Corporation. Research DivisionPublisher:
ISBN:
Category : Parallel processing (Electronic computers)
Languages : en
Pages : 16
Book Description
Fault Simulation and Test Generation for Small Delay Faults
Author: Wangqi QiuPublisher:
ISBN: 9781109849929
Category :
Languages : en
Pages : 130
Book Description
The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches.
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
Author: Sandeep K. GoelPublisher: CRC Press
ISBN: 1351833707
Category : Technology & Engineering
Languages : en
Pages : 266
Book Description
Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.
Test Generation and Fault Simulation in Digital Systems
Author: Chow Chin ChuangFault Simulation and Test Generation for Delay Faults
Author: Bejoy George OommanPublisher:
ISBN:
Category : Fault location (Engineering)
Languages : en
Pages : 116
Book Description
TGIFS
Author: Mary Helen HenskeFault Simulation and Test Generation by Fault Sampling Techniques
Author: Musaed A. Al-kharjiPublisher:
ISBN:
Category : Computers
Languages : en
Pages : 142
Book Description
Testing of Digital Systems
Author: N. K. JhaPublisher: Cambridge University Press
ISBN: 9781139437431
Category : Computers
Languages : en
Pages : 1022
Book Description
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
High Quality Test Pattern Generation and Boolean Satisfiability
Author: Stephan EggersglüßPublisher: Springer Science & Business Media
ISBN: 1441999760
Category : Technology & Engineering
Languages : en
Pages : 208
Book Description
This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly; Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model; Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.