Author: Bijesh RajamohananPublisher:
ISBN:
Category :
Languages : en
Pages : 140
Book Description
Fabrication, Characterization and Physics of III-V Tunneling Field Effect Transistors for Low Power Logic and RF Applications
Author: Bijesh RajamohananFabrication and Characterization of III-V Tunnel Field-effect Transistors for Low Voltage Logic Applications
Author: Brian R. RomanczykPublisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 216
Book Description
"With voltage scaling to reduce power consumption in scaled transistors the subthreshold swing is becoming a critical factor influencing the minimum voltage margin between the transistor on and off-states. Conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamentally limited to a 60 mV/dec swing due to the thermionic emission current transport mechanism at room temperature. Tunnel field-effect transistors (TFETs) utilize band-to-band tunneling as the current transport mechanism resulting in the potential for sub-60 mV/dec subthreshold swings and have been identified as a possible replacement to the MOSFET for low-voltage logic applications. The TFET operates as a gated p-i-n diode under reverse bias where the gate electrode is placed over the intrinsic channel allowing for modulation of the tunnel barrier thickness. When the barrier is sufficiently thin the tunneling probability increases enough to allow for significant number of electrons to tunnel from the source into the channel. To date, experimental TFET reports using III-V semiconductors have failed to produce devices that combine a steep subthreshold swing with a large enough drive current to compete with scaled CMOS. This study developed the foundations for TFET fabrication by improving an established Esaki tunnel diode process flow and extending it to include the addition of a gate electrode to form a TFET. The gating process was developed using an In0.53Ga0.57As TFET which demonstrated a minimum subthreshold slope of 100 mV/dec. To address the issue of TFET drive current an InAs/GaSb heterojunction TFET structure was investigated taking advantage of the smaller tunnel barrier height."--Abstract.
Advanced Field-Effect Transistors
Author: Dharmendra Singh YadavPublisher: CRC Press
ISBN: 1003816282
Category : Technology & Engineering
Languages : en
Pages : 370
Book Description
Advanced Field-Effect Transistors: Theory and Applications offers a fresh perspective on the design and analysis of advanced field-effect transistor (FET) devices and their applications. The text emphasizes both fundamental and new paradigms that are essential for upcoming advancement in the field of transistors beyond complementary metal–oxide–semiconductors (CMOS). This book uses lucid, intuitive language to gradually increase the comprehension of readers about the key concepts of FETs, including their theory and applications. In order to improve readers’ learning opportunities, Advanced Field-Effect Transistors: Theory and Applications presents a wide range of crucial topics: • Design and challenges in tunneling FETs • Various modeling approaches for FETs • Study of organic thin-film transistors • Biosensing applications of FETs • Implementation of memory and logic gates with FETs The advent of low-power semiconductor devices and related implications for upcoming technology nodes provide valuable insight into low-power devices and their applicability in wireless, biosensing, and circuit aspects. As a result, researchers are constantly looking for new semiconductor devices to meet consumer demand. This book gives more details about all aspects of the low-power technology, including ongoing and prospective circumstances with fundamentals of FET devices as well as sophisticated low-power applications.
Tunneling Field Effect Transistor Technology
Author: Lining ZhangPublisher: Springer
ISBN: 3319316532
Category : Technology & Engineering
Languages : en
Pages : 217
Book Description
This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency.
Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics
Author: Arun ThathacharyPublisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
With transistor technology close to its limits for power constrained scaling and the simultaneous emergence of mobile devices as the dominant driver for new scaling, a pathway to significant reduction in transistor operating voltage to 0.5V or lower is urgently sought. This however implies a fundamental paradigm shift away from mature Silicon technology. III-V compound semiconductors hold great promise in this regard due to their vastly superior electron transport properties making them prime candidates to replace Silicon in the n-channel transistor. Among the plethora of binary and ternary compounds available in the III-V space, InxGa1-xAs alloys have attracted significant interest due to their excellent electron mobility, ideally placed bandgap and mature growth technology. Simultaneously, electrostatic control mandates multi-gate transistor designs such as the FinFET at extremely scaled nodes.This dissertation describes the experimental realization of III-V FinFETs incorporating InXGa1-XAs heterostructure channels for high performance, low power logic applications. The chapters that follow present experimental demonstrations, simulations and analysis on the following aspects (a) motivation and key figures of merit driving material selection and design; (b) dielectric integration schemes for high-k metal-gate stack (HKMG) realization on InXGa1-XAs, including surface clean and passivation techniques developed for high quality interfaces; (c) novel techniques for transport (mobility) characterization in nanoscale multi-gate FET architectures with experimental demonstration on In0.7Ga0.3As nanowires; (d) Indium composition and quantum confined channel design for InXGa1-XAs FinFETs and (e) InAs heterostructure designs for high performance FinFETs. Each chapter also contains detailed benchmarking of results against state of the art demonstrations in Silicon and III-V material systems. The dissertation concludes by assessing the feasibility of InXGa1-XAs FinFET devices as n-channel Silicon replacement for low power logic technology scaling.
Organic Field Effect Transistors
Author: Ioannis KymissisPublisher: Springer Science & Business Media
ISBN: 0387921346
Category : Technology & Engineering
Languages : en
Pages : 156
Book Description
Organic Field Effect Transistors presents the state of the art in organic field effect transistors (OFETs), with a particular focus on the materials and techniques useful for making integrated circuits. The monograph begins with some general background on organic semiconductors, discusses the types of organic semiconductor materials suitable for making field effect transistors, the fabrication processes used to make integrated Circuits, and appropriate methods for measurement and modeling. Organic Field Effect Transistors is written as a basic introduction to the subject for practitioners. It will also be of interest to researchers looking for references and techniques that are not part of their subject area or routine. A synthetic organic chemist, for example, who is interested in making OFETs may use the book more as a device design and characterization reference. A thin film processing electrical engineer, on the other hand, may be interested in the book to learn about what types of electron carrying organic semiconductors may be worth trying and learning more about organic semiconductor physics.
Fundamentals of Tunnel Field-Effect Transistors
Author: Sneh SaurabhPublisher: CRC Press
ISBN: 1498767168
Category : Science
Languages : en
Pages : 306
Book Description
During the last decade, there has been a great deal of interest in TFETs. To the best authors’ knowledge, no book on TFETs currently exists. The proposed book provides readers with fundamental understanding of the TFETs. It explains the interesting characteristics of the TFETs, pointing to their strengths and weaknesses, and describes the novel techniques that can be employed to overcome these weaknesses and improve their characteristics. Different tradeoffs that can be made in designing TFETs have also been highlighted. Further, the book provides simulation example files of TFETs that could be run using a commercial device simulator.
Modeling of III-V Nanoscale Field-effect Transistors for Logic Circuits
Author: Saeroonter OhPublisher: Stanford University
ISBN:
Category :
Languages : en
Pages : 147
Book Description
As silicon CMOS technology continues to scale down its minimum critical dimension, it becomes increasingly difficult to enhance device switching speed due to fundamental limitations. Innovations in device structure and materials are pursued to accommodate improvement in performance as well as reduction in transistor size. For beyond-22-nm CMOS technology, III-V channel FETs are considered as a compelling candidate for extending the device scaling limit of low-power and high-speed operation, owing to their superb carrier transport properties and recent experimental advancements. In this thesis, device simulation, compact modeling, circuit design, circuit performance assessment and estimation of III-V logic transistors are carried out to study key considerations such as device pitch, parasitics, and the importance of PMOS for circuit-level performance. To effectively connect device characteristics with circuit design, a physics-based compact model for digital logic is constructed. The model encompasses effects such as field-confined and spatially-confined trapezoidal quantum well sub-band energies, gate leakage tunneling current and parasitic capacitance. The developed compact model contains only three fitting parameters and is verified by experiment and circuit simulations. The compact model enables other bodies of work for the purpose of circuit-level design and performance estimation. To demonstrate the capability of the model in a circuit environment we apply the compact model to composite circuits such as FO4 inverter chains and SRAM cache to evaluate and project performance and power trends for beyond-22-nm technology.
Tunnel Field-effect Transistors (TFET)
Author: Jagadesh Kumar MamidalaPublisher: John Wiley & Sons
ISBN: 1119246296
Category : Technology & Engineering
Languages : en
Pages : 205
Book Description
Research into Tunneling Field Effect Transistors (TFETs) has developed significantly in recent times, indicating their significance in low power integrated circuits. This book describes the qualitative and quantitative fundamental concepts of TFET functioning, the essential components of the problem of modelling the TFET, and outlines the most commonly used mathematical approaches for the same in a lucid language. Divided into eight chapters, the topics covered include: Quantum Mechanics, Basics of Tunneling, The Tunnel FET, Drain current modelling of Tunnel FET: The task and its challenges, Modeling the Surface Potential in TFETs, Modelling the Drain Current, and Device simulation using Technology Computer Aided Design (TCAD). The information is well organized, describing different phenomena in the TFETs using simple and logical explanations. Key features: * Enables readers to understand the basic concepts of TFET functioning and modelling in order to read, understand, and critically analyse current research on the topic with ease. * Includes state-of-the-art work on TFETs, attempting to cover all the recent research articles published on the subject. * Discusses the basic physics behind tunneling, as well as the device physics of the TFETs. * Provides detailed discussion on device simulations along with device physics so as to enable researchers to carry forward their study on TFETs. Primarily targeted at new and practicing researchers and post graduate students, the book would particularly be useful for researchers who are working in the area of compact and analytical modelling of semiconductor devices.
Design and Modeling of Low Power VLSI Systems
Author: Sharma, ManojPublisher: IGI Global
ISBN: 1522501916
Category : Technology & Engineering
Languages : en
Pages : 423
Book Description
Very Large Scale Integration (VLSI) Systems refer to the latest development in computer microchips which are created by integrating hundreds of thousands of transistors into one chip. Emerging research in this area has the potential to uncover further applications for VSLI technologies in addition to system advancements. Design and Modeling of Low Power VLSI Systems analyzes various traditional and modern low power techniques for integrated circuit design in addition to the limiting factors of existing techniques and methods for optimization. Through a research-based discussion of the technicalities involved in the VLSI hardware development process cycle, this book is a useful resource for researchers, engineers, and graduate-level students in computer science and engineering.