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Author: Yildiz Sinangil Publisher: ISBN: Category : Languages : en Pages : 193
Book Description
Today's complex systems generally target competing design goals such as maximizing performance while minimizing energy. Moreover, they have to work efficiently under changing system dynamics and application loads. Thus, for better power and performance optimization, they need to adapt to different conditions on-the-fly. In this regard, systems need to monitor important metrics such as energy consumption and performance. First part of this thesis focuses on an energy monitoring circuit design that can generate a digital representation of the absolute energy per operation of a circuit. A test-chip is fabricated in a 65nm LP CMOS process and the energy monitoring circuit is demonstrated for an SRAM application. The small power (
Author: Yildiz Sinangil Publisher: ISBN: Category : Languages : en Pages : 193
Book Description
Today's complex systems generally target competing design goals such as maximizing performance while minimizing energy. Moreover, they have to work efficiently under changing system dynamics and application loads. Thus, for better power and performance optimization, they need to adapt to different conditions on-the-fly. In this regard, systems need to monitor important metrics such as energy consumption and performance. First part of this thesis focuses on an energy monitoring circuit design that can generate a digital representation of the absolute energy per operation of a circuit. A test-chip is fabricated in a 65nm LP CMOS process and the energy monitoring circuit is demonstrated for an SRAM application. The small power (
Author: Chong-Min Kyung Publisher: Springer Science & Business Media ISBN: 9400716796 Category : Science Languages : en Pages : 295
Book Description
Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moore’s law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints. Energy-Aware System Design: Algorithms and Architectures provides state-of-the-art ideas for low power design methods from circuit, architecture to software level and offers design case studies in three fast growing areas of mobile storage, biomedical and security. Important topics and features: - Describes very recent advanced issues and methods for energy-aware design at each design level from circuit and architecture to algorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level - Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts - Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency - Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camera systems. Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.
Author: Mahmut Ersin Sinangil Publisher: ISBN: Category : Languages : en Pages : 156
Book Description
With the continuous scaling down of transistor feature sizes, the semiconductor industry faces new challenges. One of these challenges is the incessant increase of power consumption in integrated circuits. This problem has motivated the industry and academia to pay significant attention to low-power circuit design for the past two decades. Operating digital circuits at lower voltage levels was shown to increase energy efficiency and lower power consumption. Being an integral part of the digital systems, Static Random Access Memories (SRAMs), dominate the power consumption and area of modern integrated circuits. Consequently, designing low-power high density SRAMs operational at low voltage levels is an important research problem. This thesis focuses on and makes several contributions to low-power SRAM design. The trade-offs and potential overheads associated with designing SRAMs for a very large voltage range are analyzed. An 8T SRAM cell is designed and optimized for both sub-threshold and above-threshold operation. Hardware reconfigurability is proposed as a solution to power and area overheads due to peripheral assist circuitry which are necessary for low voltage operation. A 64kbit SRAM has been designed in 65nm CMOS process and the fabricated chip has been tested, demonstrating operation at power supply levels from 0.25V to 1.2V. This is the largest operating voltage range reported in 65nm semiconductor technology node. Additionally, another low voltage SRAM has been designed for the on-chip caches of a low-power H.264 video decoder. Power and performance models of the memories have been developed along with a configurable interface circuit. This custom memory implemented with the low-power architecture of the decoder provides nearly 10X power savings.
Author: Avesta Sasan Publisher: Springer ISBN: 9781461422716 Category : Technology & Engineering Languages : en Pages : 200
Book Description
This book addresses process variability and power management for embedded memories, which are becoming dominant components in today’s Systems on Chip (SoCs). It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies. The authors describe a cross-layer approach, simultaneously targeting the manufacturing of devices, the inner-design of the memory circuits, as well as the way they are architected into a system. This approach enables the design of reliable, power-efficient systems in which memories are dominating area, power, and performance.
Author: Florin Balasa Publisher: ISBN: Category : Computer storage devices Languages : en Pages : 0
Book Description
Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach presents recent computer-aided design (CAD) ideas that address memory management tasks, particularly the optimization of energy consumption in the memory subsystem. It explains how to efficiently implement CAD solutions, including theoretical methods and novel algorithms. The book covers various energy-aware design techniques, including data-dependence analysis techniques, memory size estimation methods, extensions of mapping approaches, and memory banking approaches. It shows how these techniques are used to evaluate the data storage of an application, reduce dynamic and static energy consumption, design energy-efficient address generation units, and much more. Providing an algebraic framework for memory management tasks, this book illustrates how to optimize energy consumption in memory subsystems using CAD solutions. The algorithmic style of the text should help electronic design automation (EDA) researchers and tool developers create prototype software tools for system-level exploration, with the goal to ultimately obtain an optimized architectural solution of the memory subsystem.
Author: Mohan Krishna Gopi Krishna Publisher: ISBN: Category : Languages : en Pages : 112
Book Description
Scaling of semiconductors to the 14-nanometer range and below nanometer range introduces serious design challenges that include high static power in memories and high leakage power, hindering further integration of CMOS devices. Thus, emerging devices are under intense analysis to overcome these drawbacks caused by transistor size scaling. Spintronics technology provides excellent features such as Non-Volatility, low read power, low read delay, higher scalability as well as easy integration with CMOS in comparison with SRAM memories. In addition, Carbon-Nanotube Field-Effect Transistors (CNFETs) provide superior electrical conductivity, low delay and low power consumption in comparison with conventional CMOS technology. Thus in this thesis, a unique approach to amalgamate spintronics memory technology with CNFET for logic drive in a reconfigurable computing architecture, realizing ultimate circuit performance has been discussed. A Carbon Magnetic Look-Up Table (CM-LUT) is proposed, using a Magnetic Tunnel Junction (MTJ) spintronic device as memory element and CNFET to perform the logical operations to read the data stored in the aforementioned devices. The proposed circuit is radiation resilient, ultra-low power and high speed operation and the ability to withstand high temperature gradient, Ideal for low power high performance battery operated mobile applications. In addition, the performance of hybrid drive for LUT to leverage fabrication feasibility of CMOS and performance of CNFET to realize fabrication cost effective design. The proposed 4-input 1-output CM-LUT utilizes 41 CNFETs and 16 MTJs for read operation and 35 CNFETs to perform write operation. The results for CM-LUT show 38 times energy reduction and 5.8 times faster circuit operation in comparison with CMOS-based spin-LUT.
Author: Pao-Ann Hsiung Publisher: CRC Press ISBN: 1420062670 Category : Computers Languages : en Pages : 287
Book Description
Reconfigurable systems have pervaded nearly all fields of computation and will continue to do so for the foreseeable future. Reconfigurable System Design and Verification provides a compendium of design and verification techniques for reconfigurable systems, allowing you to quickly search for a technique and determine if it is appropriate to the task at hand. It bridges the gap between the need for reconfigurable computing education and the burgeoning development of numerous different techniques in the design and verification of reconfigurable systems in various application domains. The text explains topics in such a way that they can be immediately grasped and put into practice. It starts with an overview of reconfigurable computing architectures and platforms and demonstrates how to develop reconfigurable systems. This sets up the discussion of the hardware, software, and system techniques that form the core of the text. The authors classify design and verification techniques into primary and secondary categories, allowing the appropriate ones to be easily located and compared. The techniques discussed range from system modeling and system-level design to co-simulation and formal verification. Case studies illustrating real-world applications, detailed explanations of complex algorithms, and self-explaining illustrations add depth to the presentation. Comprehensively covering all techniques related to the hardware-software design and verification of reconfigurable systems, this book provides a single source for information that otherwise would have been dispersed among the literature, making it very difficult to search, compare, and select the technique most suitable. The authors do it all for you, making it easy to find the techniques that fit your system requirements, without having to surf the net or digital libraries to find the candidate techniques and compare them yourself.
Author: Jawar Singh Publisher: Springer Science & Business Media ISBN: 1461408180 Category : Technology & Engineering Languages : en Pages : 176
Book Description
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
Author: Massoud Pedram Publisher: Springer Science & Business Media ISBN: 1402071523 Category : Computers Languages : en Pages : 533
Book Description
Presents various aspects of power-aware design methodologies, covering the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. This book includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits, systems on chip, microelectronic systems, and so on.
Author: Yildiz Sinangil
Author: Yildiz Sinangil
Author: Chong-Min Kyung
Author: Mahmut Ersin Sinangil
Author: Avesta Sasan
Author: Florin Balasa
Author: Mohan Krishna Gopi Krishna
Author: Markus Buschhoff
Author: Pao-Ann Hsiung
Author: Jawar Singh
Author: Massoud Pedram