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Author: Qingwei Li Publisher: ISBN: Category : Data encryption (Computer science) Languages : en Pages : 220
Book Description
Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is of great interest to develop low-complexity and high-speed VLSI architectures for the MIMO sphere decoders. The first part of this dissertation is focused on the low-complexity and high-speed sphere decoder design for the MIMO systems. It includes the algorithms simplification, and transformations, hardware optimization and architecture development. Specifically, we propose the layered reordered K-Best sphere decoding algorithm and dynamic K-best sphere decoding algorithm, which can significantly improve the detection performance or reduce the hardware complexity. We also present the efficient K-Best sorting architecture, which greatly simplifies the sorting operation of the K-Best SDA. In addition, we introduce the early-pruning K-Best SD scheme, which eliminates the unlikely candidate at early decoding stages, thus saves computational complexity and power consumptions. For the conventional sphere decoder design, we develop the parallel and pipeline interleaved sphere decoder architecture, which considerably increases the decoding throughput with negligible extra complexity. Finally, we design the efficient radius and list updating units for the list sphere decoder, which increases the speed of obtaining the new radius and reduces the complexity for generating the new candidate list. The wireless communication technologies are widely used for the benefits of portability and flexibility. However, the wireless security is extremely important to protect the private and sensitive information since the communication medium, the airwave, is shared and open to the public. Cryptography is the most standard and efficient way for information protection. The second part of this thesis is thus dedicated to the high-speed and efficient architecture design for the cryptography systems including ECC and Tate pairing. We propose an efficient fast architecture for the ECC in Lopez-Dahab projective coordinates. Compared with the conventional point operation implementations, the point addition and doubling operations can be significantly accelerated with reasonable hardware overhead by applying parallel processing and hardware reusing. Moreover, we develop a complexity reduction scheme and an overlapped processing architecture for the Tate pairing in characteristic three. The proposed architecture can achieve over 2 times speedup compared with conventional sequential implementations for the Duursma-Lee and Kwon-BGOS algorithms.
Author: Qingwei Li Publisher: ISBN: Category : Data encryption (Computer science) Languages : en Pages : 220
Book Description
Multiple-input multiple-output (MIMO) communication systems have recently been considered as one of the most significant technology breakthroughs for modern wireless communications, due to the higher spectral efficiency and improved link reliability. The sphere decoding algorithm (SDA) has been widely used for maximum likelihood (ML) detection in MIMO systems. It is of great interest to develop low-complexity and high-speed VLSI architectures for the MIMO sphere decoders. The first part of this dissertation is focused on the low-complexity and high-speed sphere decoder design for the MIMO systems. It includes the algorithms simplification, and transformations, hardware optimization and architecture development. Specifically, we propose the layered reordered K-Best sphere decoding algorithm and dynamic K-best sphere decoding algorithm, which can significantly improve the detection performance or reduce the hardware complexity. We also present the efficient K-Best sorting architecture, which greatly simplifies the sorting operation of the K-Best SDA. In addition, we introduce the early-pruning K-Best SD scheme, which eliminates the unlikely candidate at early decoding stages, thus saves computational complexity and power consumptions. For the conventional sphere decoder design, we develop the parallel and pipeline interleaved sphere decoder architecture, which considerably increases the decoding throughput with negligible extra complexity. Finally, we design the efficient radius and list updating units for the list sphere decoder, which increases the speed of obtaining the new radius and reduces the complexity for generating the new candidate list. The wireless communication technologies are widely used for the benefits of portability and flexibility. However, the wireless security is extremely important to protect the private and sensitive information since the communication medium, the airwave, is shared and open to the public. Cryptography is the most standard and efficient way for information protection. The second part of this thesis is thus dedicated to the high-speed and efficient architecture design for the cryptography systems including ECC and Tate pairing. We propose an efficient fast architecture for the ECC in Lopez-Dahab projective coordinates. Compared with the conventional point operation implementations, the point addition and doubling operations can be significantly accelerated with reasonable hardware overhead by applying parallel processing and hardware reusing. Moreover, we develop a complexity reduction scheme and an overlapped processing architecture for the Tate pairing in characteristic three. The proposed architecture can achieve over 2 times speedup compared with conventional sequential implementations for the Duursma-Lee and Kwon-BGOS algorithms.
Author: Leibo Liu Publisher: Springer ISBN: 9811363625 Category : Computers Languages : en Pages : 348
Book Description
This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.
Author: Chung-An Shen Publisher: ISBN: 9781267256553 Category : Languages : en Pages : 134
Book Description
In the past few years, Multiple-Input Multiple-Output (MIMO) communication has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. It has also been adopted as part of a number of industry standards such as WiMAX, LTE, and the next generation WLAN (802.11n). However, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity, including area, as well as power consumption. Thus, in MIMO systems, it is always a challenge for researchers and engineers to design a receiver structure that can achieve optimal quality of reception with manageable system complexity. In this thesis, we present efficient design for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels. We consider that the MIMO detector and the channel decoder are two major blocks and attempt to optimize them in a joint sense. First of all, we focus on the design of MIMO detector and propose two approaches. The first design presents a novel algorithm and architecture for K-Best detection. The algorithm examines a much smaller subset of points in the tree structure as compared to conventional K-Best detector; while still achieving near-optimal performance. The VLSI architecture of the detector is based on a pipelined sorter-free scheme such that high throughput and low complexity is achieved. The proposed K-Best detector is designed to support a 4 x 4 64-QAM system and can achieve an average throughput of 285.8 Mbps at 25 dB SNR with 210 Kgates area at 12.8 mW power consumption. The second design demonstrates an algorithm and VLSI architecture of combining the features of classical depth-first and breadth-first methods. Techniques to reduce complexity while providing both hard and soft output detection are also presented. This detector supports a 4 x 4 64-QAM system and can achieve an average throughput of 257.8 Mbps at 24 dB SNR with an area equivalent to 54.2 Kgates and a power consumption of 7.26 mW for hard output scheme. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW. Finally we present an approach to perform joint detection and decoding for MIMO systems which utilize convolutional codes. The BER performance of this approach is significantly better than that of systems which utilize separate detection and decoding blocks. In particular, for a reference 4x4, 16-QAM system using a rate 1/2 convolutional code with generator polynomial [247,371] and a constraint length of 8, improvements in SNR of 2.5dB and 3dB are achieved over conventional soft decoding at a BER of 10−5. The proof of concept VLSI architecture is provided and a novel way to reduce memory usage is demonstrated. The proposed design can achieve an average throughput of 216.9 Mbps at a SNR of 13 dB with area equivalent to 553 Kgates.
Author: Mahdi Shabany Publisher: ISBN: 9780494713693 Category : Languages : en Pages : 400
Book Description
The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for 4x4 MIMO systems in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this thesis introduces a novel scalable pipelined VLSI architecture for a 4 x 4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The proposed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13mum CMOS, it operates at a significantly higher throughput (5.8x better) than currently reported schemes and occupies 0.95 mm2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no performance loss. It achieves an SNR-independent decoding throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and Long Term Evolution (LTE) systems. The measurements confirm that this design consumes 3.0x less energy/bit compared to the previous best design.
Author: Publisher: ISBN: Category : Languages : en Pages :
Book Description
The efficient high-throughput VLSI implementation of near-optimal multiple-input multiple-output (MIMO) detectors for 4x4 MIMO systems in high-order quadrature amplitude modulation (QAM) schemes has been a major challenge in the literature. To address this challenge, this thesis introduces a novel scalable pipelined VLSI architecture for a 4x4 64-QAM MIMO receiver based on K-Best lattice decoders. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in K clock cycles. The proposed architecture has a fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distributed sorters, and is scalable to a higher number of antennas/constellation orders. Fabricated in 0.13um CMOS, it operates at a significantly higher throughput (5.8x better) than currently reported schemes and occupies 0.95 mm2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no performance loss. It achieves an SNR-independent decoding throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and Long Term Evolution (LTE) systems. The measurements confirm that this design consumes 3.0x less energy/bit compared to the previous best design.
Author: Pankaj Bhagawat Publisher: ISBN: Category : Languages : en Pages :
Book Description
Ever increasing demand for higher data rates and better Quality of Service (QoS) for a growing number of users requires new transceiver algorithms and architectures to better exploit the available spectrum and to efficiently counter the impairments of the radio channel. Multiple-Input Multiple-Output (MIMO) communication systems employ multiple antennas at both transmitter and at the receiver to meet the requirements of next-generation wireless systems. It is a promising technology to provide increased data rates while not involving an equivalent increase in the spectral requirements. However, practical implementation of MIMO detectors poses a significant challenge and has been consistently identified as the major bottleneck for realizing the full potential that multiple antenna systems promise. Furthermore, in order to make judicious use of the available bandwidth, the baseband units have to dynamically adapt to different modes (modulation schemes, code rates etc) of operations. Flexibility and high throughput requirements often place conflicting demands on the Very Large Scale Integration (VLSI) system designer. The major focus of this dissertation is to present efficient VLSI architectures for configurable MIMO detectors that can serve as accelerators to enable the realization of next generation wireless devices feasible. Both, hard output and soft output detector architectures are considered.
Author: Qingwei Li
Author: Qingwei Li
Author: Leibo Liu
Author: Sushma Prasad (Honnavara)
Author: 
Author: Chung-An Shen
Author: Mahdi Shabany
Author: 
Author: 馮紹惟
Author: Pankaj Bhagawat
Author: Ravi Somnath Jenkal