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Author: Publisher: ISBN: Category : Languages : en Pages : 116
Book Description
The high resolution direction of arrival (DOA) estimation has been an important area of research for a number of years. Many researchers have developed a variety of algorithms to estimate the direction of arrival. Another important aspect of the DOA estimation area is the development of high speed hardware capable of computing the DOA in real time. In this research we have first focussed on the development of parallel architecture for multiple signal classification (MUSIC) and estimation os signal parameters by rotational invariance technique (ESPRIT) algorithms for the narrow band sources. These algorithms are substituted with computationally efficient modules and converted to pipelined and parallel algorithms. For example one important computation of eigendecomposition of the covariance matrix has been performed using Householders transformations and QR method.
Author: Publisher: ISBN: Category : Languages : en Pages : 116
Book Description
The high resolution direction of arrival (DOA) estimation has been an important area of research for a number of years. Many researchers have developed a variety of algorithms to estimate the direction of arrival. Another important aspect of the DOA estimation area is the development of high speed hardware capable of computing the DOA in real time. In this research we have first focussed on the development of parallel architecture for multiple signal classification (MUSIC) and estimation os signal parameters by rotational invariance technique (ESPRIT) algorithms for the narrow band sources. These algorithms are substituted with computationally efficient modules and converted to pipelined and parallel algorithms. For example one important computation of eigendecomposition of the covariance matrix has been performed using Householders transformations and QR method.
Author: M. M. Jamali Publisher: ISBN: Category : Languages : en Pages : 138
Book Description
One of today's problems in signal processing is the identification of direction-of-arrival (DOA) for multiple broad-band sources. Many algorithms have been proposed in the literature, however, the algorithms are highly complex and require a lot of computing power. New technologies in the past two decades have decreased the cost of digital hardware, and its speed has increased to such an extent that digital signal processing has replaced a great deal of analog signal processing. This thesis presents a digital-domain parallel-pipelined architecture capable of computing the DOA of multiple broad-band sources in real-time. Broad-Band Signal-Subspace Spatial-Spectrum (BASS-ALE) Estimation algorithm has been selected for DOA estimation and has been simulated and verified through computer software programs. The BASS-ALE algorithm has been modified and parallelized. The parallel algorithm has been mapped on an architecture which is suitable for real-time computation.
Author: Publisher: ISBN: Category : Languages : en Pages : 92
Book Description
The high resolution direction-of-arrival (DOA) estimation is important in many sensor systems. It is based on the processing of the received signal and extracting the desired parameters of the DOA of plane waves. Many approaches have been used for the purpose of implementing the function required for the DOA estimation. The Multiple Signal Classification (MUSIC) and the Estimation of Signal Parameters by Rotational Invariance techniques (ESPRIT) algorithms are two novel approaches used recently to provide asymptotically unbiased and efficient estimates of the DOA. They are believed to be promising and appropriate for hardware implementation for real time applications. They estimate the so called signal subspace from the array measurements. The parameters of interest (i.e. determining of the DOA) are then estimated from the intersection between the array manifold and the estimated subspace.
Author: Amin Jarrah Publisher: ISBN: Category : Computer engineering Languages : en Pages : 245
Book Description
The applications of digital signal processing continue to expand and use in many different areas such as signal processing, radar tracking, image processing, medical imaging, video broadcasting, and control algorithms for sensor array processing. Most of the signal processing applications are intensive and may not achieve the real time requirements. However, the Multi-core phenomenon has been embraced by almost all processor manufacturers and the road to the future is through parallel processing. Now we have many parallel processing platforms that developed for high performance such as: 1) Multi-Core/Many-Cores 2) Graphic Processing Units (GPU) 3) Field Programmable Gate Arrays (FPGA) This research work involves developing optimized parallel architectures of many signal processing applications such as Extensive Cancellation Algorithm (ECA), Direct Data Domain (D3), Block Compressive Sampling Matching Pursuit algorithm (BCoSaMP), video processing, Discrete Wavelet Transform (DWT), Particle Filter (PF), and Iterative Hard Thresholding (IHT) on different platforms such as Multi-core, FPGA and GPU. This is performed by exploring opportunities of any computation and storage that can be eliminated to achieve high performance and meet its real time requirements. Different techniques and ideas have also been derived from different advanced fields to increase the intelligibility and the usefulness of our research. A new innovative generalized method is proposed which can be very helpful for many researchers in various areas. Then, the applications have been moved higher ordering through implementing interfaces. This makes it adaptable by specifying all the input parameters of a certain application and fast prototyping through different performance evaluations. We propose and exploit many parallelization methods and optimization techniques in order to improve the latency, hardware usage, power consumption, cost, and reliability. These parallelization methods predict the data path and the control unit of the application processes. Also, the applications examine into numerical algorithms approaches to provide a transition from the research theory to the practice and to enhance the computational and resource requirements by adapting the certain algorithm for high performance applications. We exploit techniques coupled with high level synthesis tools by enabling rapid development to generate efficient parallel codes from high-level problem descriptions. This will reduce the design time, increase the productivity, improve the reliability, and enable exploration of the design space. Approaches will include optimizations based on mathematical and/or statistical reasoning, set theory, logic, and auto-tuning techniques. Hardware software co-design for these applications has been performed that pushes performance and energy efficiency while reducing cost, area, and overhead. This has been accomplished by developing a tool called Radar Signal Processing Tool (RSPT). RSPT allows the designer to auto-generate fully optimized VHDL representation of any of these signal processing algorithms by specifying many user input parameters through Graphic User Interface (GUI). This will offer great flexibility in designing signal processing applications for a System on Chip (SoC) without having to write a single line of VHDL code. RSPT also communicates with Xilinx toolset to check for the available FPGA parts installed with the Xilinx toolset and for executing the VHDL synthesis command chain. Moreover, it utilizes optimization techniques such as pipelining, code in-lining, loop unrolling, loops merging, and dataflow techniques by allowing the concurrent execution of operations to improve throughput and latency. Finally, RSPT provides the designer a feedback on various performance parameters such as occupied slices, maximum frequency, and dynamic range. This offers the designer the ability to make any adjustments to the algorithm component until the desired performance of the overall SoC is achieved. Parallel approach of IR Video processing is also proposed as it widely used in many numerous processing applications and not achieve the real time requirements. Analysis and assessment of the energy dissipation for heterogeneous Network on Chip (NoC) based Multiprocessor System on Chip (MPSoC) platform running a video application are performed. It identifies the latency, area, and energy bottlenecks of the entire heterogeneous platform including processors, interconnection wires, routers, memory, and caches etc. Also, we propose a new modeling and simulation approach regarding the channel width and buffer sizing which have a strong impact on the performance and the overhead of the chip. This approach monitors the state of each link in the NoC topology. Then, based on the congestion spot and the critical path we can optimize the design by changing channel width and buffer size until achieving the desired performance.
Author: David B. Kirk Publisher: Newnes ISBN: 0123914183 Category : Computers Languages : en Pages : 519
Book Description
Programming Massively Parallel Processors: A Hands-on Approach, Second Edition, teaches students how to program massively parallel processors. It offers a detailed discussion of various techniques for constructing parallel programs. Case studies are used to demonstrate the development process, which begins with computational thinking and ends with effective and efficient parallel programs. This guide shows both student and professional alike the basic concepts of parallel programming and GPU architecture. Topics of performance, floating-point format, parallel patterns, and dynamic parallelism are covered in depth. This revised edition contains more parallel programming examples, commonly-used libraries such as Thrust, and explanations of the latest tools. It also provides new coverage of CUDA 5.0, improved performance, enhanced development tools, increased hardware support, and more; increased coverage of related technology, OpenCL and new material on algorithm patterns, GPU clusters, host programming, and data parallelism; and two new case studies (on MRI reconstruction and molecular visualization) that explore the latest applications of CUDA and GPUs for scientific research and high-performance computing. This book should be a valuable resource for advanced students, software engineers, programmers, and hardware engineers. - New coverage of CUDA 5.0, improved performance, enhanced development tools, increased hardware support, and more - Increased coverage of related technology, OpenCL and new material on algorithm patterns, GPU clusters, host programming, and data parallelism - Two new case studies (on MRI reconstruction and molecular visualization) explore the latest applications of CUDA and GPUs for scientific research and high-performance computing
Author: Ákos Zarándy Publisher: Springer Science & Business Media ISBN: 1441964754 Category : Technology & Engineering Languages : en Pages : 311
Book Description
Focal-plane sensor-processor imager devices are sensor arrays and processor arrays embedded in each other on the same silicon chip. This close coupling enables ultra-fast processing even on tiny, low power devices, because the slow and energetically expensive transfer of the large amount of sensory data is eliminated. This technology also makes it possible to produce locally adaptive sensor arrays, which can (similarly to the human retina) adapt to the large dynamics of the illumination in a single scene This book focuses on the implementation and application of state-of-the-art vision chips. It provides an overview of focal plane chip technology, smart imagers and cellular wave computers, along with numerous examples of current vision chips, 3D sensor-processor arrays and their applications. Coverage includes not only the technology behind the devices, but also their near- and mid-term research trends.
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