Author: Richard J. BurgessPublisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
Development of a CMOS Iddq Testing Environment
Author: Richard J. BurgessIntroduction to IDDQ Testing
Author: S. ChakravartyPublisher: Springer Science & Business Media
ISBN: 146156137X
Category : Technology & Engineering
Languages : en
Pages : 336
Book Description
Testing techniques for VLSI circuits are undergoing many exciting changes. The predominant method for testing digital circuits consists of applying a set of input stimuli to the IC and monitoring the logic levels at primary outputs. If, for one or more inputs, there is a discrepancy between the observed output and the expected output then the IC is declared to be defective. A new approach to testing digital circuits, which has come to be known as IDDQ testing, has been actively researched for the last fifteen years. In IDDQ testing, the steady state supply current, rather than the logic levels at the primary outputs, is monitored. Years of research suggests that IDDQ testing can significantly improve the quality and reliability of fabricated circuits. This has prompted many semiconductor manufacturers to adopt this testing technique, among them Philips Semiconductors, Ford Microelectronics, Intel, Texas Instruments, LSI Logic, Hewlett-Packard, SUN microsystems, Alcatel, and SGS Thomson. This increase in the use of IDDQ testing should be of interest to three groups of individuals associated with the IC business: Product Managers and Test Engineers, CAD Tool Vendors and Circuit Designers. Introduction to IDDQ Testing is designed to educate this community. The authors have summarized in one volume the main findings of more than fifteen years of research in this area.
IDDQ Testing of VLSI Circuits
Author: Ravi K. GulatiPublisher: Springer Science & Business Media
ISBN: 1461531462
Category : Computers
Languages : en
Pages : 121
Book Description
Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Author: Manoj SachdevPublisher: Springer Science & Business Media
ISBN: 0387465472
Category : Technology & Engineering
Languages : en
Pages : 343
Book Description
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Iddq Testing for CMOS VLSI
Author: Rochit RajsumanPublisher: Artech House Publishers
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 216
Book Description
This book discusses in detail the correlation between physical defects and logic faults, and shows you how Iddq testing locates these defects. The book provides planning guidelines and optimization methods and is illustrated with numerous examples ranging from simple circuits to extensive case studies.
IDDQ Testing in Low Power Supply CMOS Circuits
Author: Mindy WenPublisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 96
Book Description
CMOS Test and Evaluation
Author: Manjul BhushanPublisher: Springer
ISBN: 1493913492
Category : Technology & Engineering
Languages : en
Pages : 431
Book Description
CMOS Test and Evaluation: A Physical Perspective is a single source for an integrated view of test and data analysis methodology for CMOS products, covering circuit sensitivities to MOSFET characteristics, impact of silicon technology process variability, applications of embedded test structures and sensors, product yield, and reliability over the lifetime of the product. This book also covers statistical data analysis and visualization techniques, test equipment and CMOS product specifications, and examines product behavior over its full voltage, temperature and frequency range.
Iddq Testing of a CMOS 10-bit Charge Scaling Digital-to-analog Converter
Author: Srinivas Rao AluriAn Approach to Simultaneous Logic and IDDQ Testing of CMOS ICs
Author: Md. Aktaf-Ul-AminPublisher:
ISBN:
Category :
Languages : en
Pages : 6
Book Description
This paper presents an approach to simultaneous logic and IDDQ testing which are crucial in verifying the functionality and improving the reliability of CMOS ICs. Work presented in this paper involves the design of an off-chip current sensor and a compatible test processor for the aforesaid purpose. The sensor is an analog circuit and the test processor is a digital circuit. The performance of both the sensor and the test processor has been verified through computer simulation. [Author's abstract].
Author: Lan Rao