Development and Characterization of a Wafer-scale Packaging Technique for Stable, Large Lateral Deflection MEMS PDF Download

Author: Matthew William Messana
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Languages : en
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Book Description
Microelectromechanical systems (MEMS) are very popular in our everyday lives. They are becoming more ubiquitous, showing in automobiles, cell phones, projectors, toys and many other places. The packaging of these devices is critical to their performance and reliability and must be carefully considered in their overall system design. Due to strict requirements and the fragile nature of these devices, the packaging often represents a significant portion of the total cost of a MEMS product. Stanford University, jointly with Bosch, developed a wafer-scale encapsulation method in which MEMS devices are encapsulated as a part of their fabrication. This process, now used by SiTime, has been dubbed the 'epi-seal' process by virtue of its use of an epitaxial silicon reactor to seal the cavities containing the devices. The MEMS devices are cleaned in situ in the epitaxial silicon reactor just prior to sealing with silicon, resulting in a package environment that is very clean and stable. Because this is a batch process, the overall packaged device cost is very low. One significant limitation with this process, however, is that devices are limited to small (less than 2[Mu]m) trenches, thus prohibiting large displacements and the use of common MEMS structures such as comb drives. In this dissertation, I will discuss two methods for expanding the design rules of the epi-seal process to include large lateral deflection structures, while still maintaining the desirable qualities of the original process. The first method employs a thick SiO2 deposition and its subsequent planarization to fill in all of the large trenches. The second method involves fusion bonding a sacrificial wafer to a silicon-on-insulator (SOI) wafer, in which devices are already etched, bridging over the trenches. The sacrificial wafer is thinned via grinding and polishing, similar to the fabrication of an SOI. Cavities are vented through the thinned wafer and devices released using HF vapor. Like the epi-seal process, the devices are then cleaned and sealed in the epitaxial silicon reactor for both of these processes. Many widely varying devices were produced using this process in the Stanford Nanofabrication Facility (SNF) with high yield. I will discuss some of these devices and how we used them to characterize the packaging.