Author: Dinesh PatilPublisher:
ISBN:
Category :
Languages : en
Pages : 137
Book Description
Design of Robust Energy-efficient Digital Circuits Using Geometric Programming
Author: Dinesh PatilGeometric Programming for Design Equation Development and Cost/Profit Optimization (with illustrative case study problems and solutions), Third Edition
Author: Robert CreesePublisher: Springer Nature
ISBN: 3031793765
Category : Technology & Engineering
Languages : en
Pages : 194
Book Description
Geometric Programming is used for cost minimization, profit maximization, obtaining cost ratios, and the development of generalized design equations for the primal variables. The early pioneers of geometric programming—Zener, Duffin, Peterson, Beightler, Wilde, and Phillips—played important roles in its development. Five new case studies have been added to the third edition. There are five major sections: (1) Introduction, History and Theoretical Fundamentals; (2) Cost Minimization Applications with Zero Degrees of Difficulty; (3) Profit Maximization Applications with Zero Degrees of Difficulty; (4) Applications with Positive Degrees of Difficulty; and (5) Summary, Future Directions, and Geometric Programming Theses & Dissertations Titles. The various solution techniques presented are the constrained derivative approach, condensation of terms approach, dimensional analysis approach, and transformed dual approach. A primary goal of this work is to have readers develop more case studies and new solution techniques to further the application of geometric programming.
Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits
Author: Nele ReyndersPublisher: Springer
ISBN: 3319161369
Category : Technology & Engineering
Languages : en
Pages : 207
Book Description
This book focuses on increasing the energy-efficiency of electronic devices so that portable applications can have a longer stand-alone time on the same battery. The authors explain the energy-efficiency benefits that ultra-low-voltage circuits provide and provide answers to tackle the challenges which ultra-low-voltage operation poses. An innovative design methodology is presented, verified, and validated by four prototypes in advanced CMOS technologies. These prototypes are shown to achieve high energy-efficiency through their successful functionality at ultra-low supply voltages.
Robust Design of Variation-sensitive Digital Circuits
Author: Hassan MostafaPublisher:
ISBN:
Category :
Languages : en
Pages : 226
Book Description
The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design. Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS technology. The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while taking the process variations impact and robustness requirements into account. Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability (NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and test chip measurements using triple-well 65nm CMOS technology. The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results and test chip measurements using 65nm CMOS technology.
Geometric Programming for Communication Systems
Author: Mung ChiangPublisher: Now Publishers Inc
ISBN: 9781933019093
Category : Computers
Languages : en
Pages : 172
Book Description
Recently Geometric Programming has been applied to study a variety of problems in the analysis and design of communication systems from information theory and queuing theory to signal processing and network protocols. Geometric Programming for Communication Systems begins its comprehensive treatment of the subject by providing an in-depth tutorial on the theory, algorithms, and modeling methods of Geometric Programming. It then gives a systematic survey of the applications of Geometric Programming to the study of communication systems. It collects in one place various published results in this area, which are currently scattered in several books and many research papers, as well as to date unpublished results. Geometric Programming for Communication Systems is intended for researchers and students who wish to have a comprehensive starting point for understanding the theory and applications of geometric programming in communication systems.
Analysis and Design of Energy-efficient Digital Circuits
Author: Bart Richard ZeydelDissertation Abstracts International
Author: Publisher:
ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 868
Book Description
Optimization in Electrical Engineering
Author: Mohammad FathiPublisher: Springer
ISBN: 3030053091
Category : Technology & Engineering
Languages : en
Pages : 174
Book Description
This textbook provides students, researchers, and engineers in the area of electrical engineering with advanced mathematical optimization methods. Presented in a readable format, this book highlights fundamental concepts of advanced optimization used in electrical engineering. Chapters provide a collection that ranges from simple yet important concepts such as unconstrained optimization to highly advanced topics such as linear matrix inequalities and artificial intelligence-based optimization methodologies. The reader is motivated to engage with the content via numerous application examples of optimization in the area of electrical engineering. The book begins with an extended review of linear algebra that is a prerequisite to mathematical optimization. It then precedes with unconstrained optimization, convex programming, duality, linear matrix inequality, and intelligent optimization methods. This book can be used as the main text in courses such as Engineering Optimization, Convex Engineering Optimization, Advanced Engineering Mathematics and Robust Optimization and will be useful for practicing design engineers in electrical engineering fields. Author provided cases studies and worked examples are included for student and instructor use.
Geometric Programming and Signal Flow Graph Assisted Design of Interconnect and Analog Circuits
Author: 張永泰Publisher: Open Dissertation Press
ISBN: 9781361470046
Category :
Languages : en
Pages :
Book Description
This dissertation, "Geometric Programming and Signal Flow Graph Assisted Design of Interconnect and Analog Circuits" by 張永泰, Wing-tai, Cheung, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. Abstract: Abstract of thesis entitled Geometric Programming and Signal Flow Graph Assisted Design of Interconnect and Analog Circuits Submitted by CHEUNG, Wing Tai for the degree of Master of Philosophy at the University of Hong Kong in August 2007 Very-large-scale integration (VLSI) interconnects and analog circuits play an impor- tant role in modern integrated circuit (IC) development. To ensure the IC design meets the time-to-market with viable production cost, the design stages are relying more heav- ily on computer-aided design (CAD) automation. Employing fast and global optimization techniques in the design stage constitutes a versatile way to facilitate the best circuit per- formance within a fast design cycle. This thesis features two main techniques, namely Geometric Programming (GP) and Signal Flow Graph (SFG), which assist the design of electronic circuits. First, the power op- timization of a repeater-inserted interconnects using GP is investigated. The ever-shrinking interconnect sizes and the quest for high-speed VLSI circuits have posed significant chal- lenges to the design of interconnect wires. Motivated by this problem, an automated design flow utilizing GP optimization is proposed for repeater insertion under power dissipation constraints. Furthermore, the development of low-noise amplifiers (LNAs) using the GP framework is proposed. The objective of this optimization approach is to minimize the noise figure of an LNA, subject to resonant frequency and input impedance matching. Byemploying the common source inductive degenerated LNA, globally optimal circuits satis- fying design constraints and specifications are obtained with high computational efficiency. An enhancement of the proposed automated design flow with linearity constraints made possible by monomial curve fitting technique, thus conforming to the GP standard form and allowing its fast deployment, is also introduced. The second part of this thesis addresses graphical-assisted design in electronic circuits. First, a parallel switched-capacitor resonant converter (SCRC) structure which fully uti- lizes the pulse switching period through interleaving technique is proposed. Signal Flow Graph (SFG) is utilized for the design of SCRC. The operations of the power converters and the directions of signal flow are visualized and analyzed using flow graph techniques. Conversion of the graphical representation to mathematical representation, such as transfer function, uses the Mason Rule. The proposed SCRC architecture demonstrates an excellent efficiency and load regulation, which are then verified using PSPICE simulations. An abstract of exactly 329 words DOI: 10.5353/th_b3955852 Subjects: Geometric programming Electronic circuit design Integrated circuits - Very large scale integration
Closing the Power Gap between ASIC & Custom
Author: David ChinneryPublisher: Springer Science & Business Media
ISBN: 0387689532
Category : Technology & Engineering
Languages : en
Pages : 392
Book Description
Explains how to use low power design in an automated design flow, and examine the design time and performance trade-offs Includes the latest tools and techniques for low power design applied in an ASIC design flow Focuses on low power in an automated design methodology, a much neglected area