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Author: Yifei Zhang Publisher: ISBN: Category : Languages : en Pages : 254
Book Description
Low-density parity-check (LDPC) codes have been intensively studied in the past decade for their capacity-approaching performance. LDPC code implementation complexity and the error-rate floor are still two significant unsolved issues which prevent their application in some important communication systems. In this dissertation, we make efforts toward solving these two problems by introducing the design of a class of LDPC codes called structured irregular repeat-accumulate (S-IRA) codes. These S-IRA codes combine several advantages of other types of LDPC codes, including low encoder and decoder complexities, flexibility in design, and good performance on different channels. It is also demonstrated in this dissertation that the S-IRA codes are suitable for rate-compatible code family design and a multi-rate code family has been designed which may be implemented with a single encoder/decoder. The study of the error floor problem of LDPC codes is very difficult because simulating LDPC codes on a computer at very low error rates takes an unacceptably long time. To circumvent this difficulty, we implemented a universal quasi-cyclic LDPC decoder on a field programmable gate array (FPGA) platform. This hardware platform accelerates the simulations by more than 100 times as compared to software simulations. We implemented two types of decoders with partially parallel architectures on the FPGA: a circulant-based decoder and a protograph-based decoder. By focusing on the protograph-based decoder, different soft iterative decoding algorithms were implemented. It provides us with a platform for quickly evaluating and analyzing different quasi-cyclic LDPC codes, including the S-IRA codes. A universal decoder architecture is also proposed which is capable of decoding of an arbitrary LDPC code, quasi-cyclic or not. Finally, we studied the low-floor problem by focusing on one example S-IRA code. We identified the weaknesses of the code andproposed several techniques to lower the error floor. We successfully demonstrated in hardware that it is possible to lower the floor substantially by encoder and decoder modifications, but the best solution appeared to be an outer BCH code.
Author: Yifei Zhang Publisher: ISBN: Category : Languages : en Pages : 254
Book Description
Low-density parity-check (LDPC) codes have been intensively studied in the past decade for their capacity-approaching performance. LDPC code implementation complexity and the error-rate floor are still two significant unsolved issues which prevent their application in some important communication systems. In this dissertation, we make efforts toward solving these two problems by introducing the design of a class of LDPC codes called structured irregular repeat-accumulate (S-IRA) codes. These S-IRA codes combine several advantages of other types of LDPC codes, including low encoder and decoder complexities, flexibility in design, and good performance on different channels. It is also demonstrated in this dissertation that the S-IRA codes are suitable for rate-compatible code family design and a multi-rate code family has been designed which may be implemented with a single encoder/decoder. The study of the error floor problem of LDPC codes is very difficult because simulating LDPC codes on a computer at very low error rates takes an unacceptably long time. To circumvent this difficulty, we implemented a universal quasi-cyclic LDPC decoder on a field programmable gate array (FPGA) platform. This hardware platform accelerates the simulations by more than 100 times as compared to software simulations. We implemented two types of decoders with partially parallel architectures on the FPGA: a circulant-based decoder and a protograph-based decoder. By focusing on the protograph-based decoder, different soft iterative decoding algorithms were implemented. It provides us with a platform for quickly evaluating and analyzing different quasi-cyclic LDPC codes, including the S-IRA codes. A universal decoder architecture is also proposed which is capable of decoding of an arbitrary LDPC code, quasi-cyclic or not. Finally, we studied the low-floor problem by focusing on one example S-IRA code. We identified the weaknesses of the code andproposed several techniques to lower the error floor. We successfully demonstrated in hardware that it is possible to lower the floor substantially by encoder and decoder modifications, but the best solution appeared to be an outer BCH code.
Author: William Ryan Publisher: Cambridge University Press ISBN: 1139483013 Category : Technology & Engineering Languages : en Pages : 709
Book Description
Channel coding lies at the heart of digital communication and data storage, and this detailed introduction describes the core theory as well as decoding algorithms, implementation details, and performance analyses. In this book, Professors Ryan and Lin provide clear information on modern channel codes, including turbo and low-density parity-check (LDPC) codes. They also present detailed coverage of BCH codes, Reed-Solomon codes, convolutional codes, finite geometry codes, and product codes, providing a one-stop resource for both classical and modern coding techniques. Assuming no prior knowledge in the field of channel coding, the opening chapters begin with basic theory to introduce newcomers to the subject. Later chapters then extend to advanced topics such as code ensemble performance analyses and algebraic code design. 250 varied and stimulating end-of-chapter problems are also included to test and enhance learning, making this an essential resource for students and practitioners alike.
Author: Xiaoheng Chen Publisher: ISBN: 9781124906669 Category : Languages : en Pages :
Book Description
Since the rediscovery of low-density parity-check (LDPC) codes in the late 1990s, tremendous progress has been made in code construction and design, decoding algorithms, and decoder implementation of these capacity-approaching codes. Recently, LDPC codes are considered for applications such as high-speed satellite and optical communications, the hard disk drives, and high-density flash memory based storage systems, which require that the codes are free of error-floor down to bit error rate (BER) as low as 10−12 to 10−15. FPGAs are usually used to evaluate the error performance of codes, since one can exploit the finite word length and extremely high internal memory bandwidth of an FPGA. Existing FPGA-based LDPC decoders fail to utilize the configurability and read-first mode of embedded memory in the FPGAs, and thus result in limited throughput and codes sizes. Four optimization techniques, i.e., vectorization, folding, message relocation, and circulant permutation matrix (CPM) sharing, are proposed to improve the throughput, scalability, and efficiency of FPGA-based decoders. Also, a semi-automatic CAD tool called QCSYN (Quasi-Cyclic LDPC decoder SYNthesis) is designed to shorten the implementation time of decoders. Using the above techniques, a high-rate (16129,15372) code is shown to have no error-floor down to the BER of 10−14. Also, it is very difficult to construct codes that do not exhibit an error floor down to 10−15 or so. Without detailed knowledge of dominant trapping sets, a backtracking-based reconfigurable decoder is designed to lower the error floor of a family of structurally compatible quasi-cyclic LDPC codes by one to two orders of magnitudes. Hardware reconfigurability is another significant feature of LDPC decoders. A tri-mode decoder for the (4095,3367) Euclidean geometry code is designed to work with three compatible binary message passing decoding algorithms. Note that this code contains 262080 edges (21.3 times of the (2048,1723) 10GBASE-T code) in its Tanner graph and is the largest code ever implemented. Besides, an efficient QC-LDPC Shift Network (QSN) is proposed to reduce the interconnect delay and control logic of circular shift network, a core component in the reconfigurable decoder that supports a family of structurally compatible codes. The interconnect delay and control logic area are reduced by a factor of 2.12 and 8, respectively. Non-binary LDPC codes are effective in combating burst errors. Using the power representation of the elements in the Galois field to organize both intrinsic and extrinsic messages, we present an efficient decoder architecture for non-binary QC-LDPC codes. The proposed decoder is reconfigurable and can be used to decode any code of a given field size. The decoder supports both regular and irregular non-binary QC-LDPC codes. Using a practical metric of throughput per unit area, the proposed implementation outperforms the best implementations published in research literature to date.
Author: Todd K. Moon Publisher: John Wiley & Sons ISBN: 1119567491 Category : Computers Languages : en Pages : 999
Book Description
Providing in-depth treatment of error correction Error Correction Coding: Mathematical Methods and Algorithms, 2nd Edition provides a comprehensive introduction to classical and modern methods of error correction. The presentation provides a clear, practical introduction to using a lab-oriented approach. Readers are encouraged to implement the encoding and decoding algorithms with explicit algorithm statements and the mathematics used in error correction, balanced with an algorithmic development on how to actually do the encoding and decoding. Both block and stream (convolutional) codes are discussed, and the mathematics required to understand them are introduced on a "just-in-time" basis as the reader progresses through the book. The second edition increases the impact and reach of the book, updating it to discuss recent important technological advances. New material includes: Extensive coverage of LDPC codes, including a variety of decoding algorithms A comprehensive introduction to polar codes, including systematic encoding/decoding and list decoding An introduction to fountain codes Modern applications to systems such as HDTV, DVBT2, and cell phones Error Correction Coding includes extensive program files (for example, C++ code for all LDPC decoders and polar code decoders), laboratory materials for students to implement algorithms, and an updated solutions manual, all of which are perfect to help the reader understand and retain the content. The book covers classical BCH, Reed Solomon, Golay, Reed Muller, Hamming, and convolutional codes which are still component codes in virtually every modern communication system. There are also fulsome discussions of recently developed polar codes and fountain codes that serve to educate the reader on the newest developments in error correction.
Author: Martin Tomlinson Publisher: Springer ISBN: 3319511033 Category : Technology & Engineering Languages : en Pages : 527
Book Description
This book discusses both the theory and practical applications of self-correcting data, commonly known as error-correcting codes. The applications included demonstrate the importance of these codes in a wide range of everyday technologies, from smartphones to secure communications and transactions. Written in a readily understandable style, the book presents the authors’ twenty-five years of research organized into five parts: Part I is concerned with the theoretical performance attainable by using error correcting codes to achieve communications efficiency in digital communications systems. Part II explores the construction of error-correcting codes and explains the different families of codes and how they are designed. Techniques are described for producing the very best codes. Part III addresses the analysis of low-density parity-check (LDPC) codes, primarily to calculate their stopping sets and low-weight codeword spectrum which determines the performance of th ese codes. Part IV deals with decoders designed to realize optimum performance. Part V describes applications which include combined error correction and detection, public key cryptography using Goppa codes, correcting errors in passwords and watermarking. This book is a valuable resource for anyone interested in error-correcting codes and their applications, ranging from non-experts to professionals at the forefront of research in their field. This book is open access under a CC BY 4.0 license.
Author: Ricardo Reis Publisher: Springer Science & Business Media ISBN: 0387895574 Category : Computers Languages : en Pages : 315
Book Description
This book contains extended and revised versions of the best papers that were presented during the fifteenth edition of the IFIP/IEEE WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 15th conference was held at the Georgia Institute of Technology, Atlanta, USA (October 15-17, 2007). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt, Perth and Nice. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5 and by the IEEE Council on Electronic Design Automation (CEDA), is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI-SoC conferences aim to address these exciting new issues.
Author: Radek Silhavy Publisher: Springer ISBN: 3030198138 Category : Technology & Engineering Languages : en Pages : 370
Book Description
This book discusses novel intelligent-system algorithms and methods in cybernetics, presenting new approaches in the field of cybernetics and automation control theory. It constitutes the proceedings of the Cybernetics and Automation Control Theory Methods in Intelligent Algorithms Section of the 8th Computer Science On-line Conference 2019 (CSOC 2019), held on-line in April 2019.
Author: Aliazam Abbasfar Publisher: Springer Science & Business Media ISBN: 1402063911 Category : Technology & Engineering Languages : en Pages : 94
Book Description
This book introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps).
Author: Yifei Zhang
Author: Yifei Zhang
Author: William Ryan
Author: Xiaoheng Chen
Author: Todd K. Moon
Author: 
Author: Martin Tomlinson
Author: Stallings
Author: Ricardo Reis
Author: Radek Silhavy
Author: Aliazam Abbasfar